Hi folks, A couple of questions regarding the https://github.com/projectacrn/acrn-kernel repository: * Where can I find instructions on how to use it? * Should we switch the Clear Linux reference

Hi Geoffroy, To build SOS using the acrn-kernel repo, you could follow the instructions on this wiki page [1]. Though it provides flexibility to customize your own kernel, I am concerned to replace

Hi folks, I have come across a guest behavior wherein guest updates the ioapic tables while the interrupt is unmasked. A condition in hypervisor at the following location: is preventing the

Hi Abdul, May I ask in which OS you saw the behavior ( update IOAPIC entry without mask it)? Thanks, Anthony

Hi, Abdul, It’s designed for supporting pass-thru devices, when vioapic RTE got unmask, it will go to check if a pass-thru entry valid for this vioapic pin, if yes, then native IOAPIC will got

Hi Anthony, I am using sos kernel from https://github.com/projectacrn/acrn-kernel/commits/master commit-id: 9bba4539d654af06d4642f9773e5444da7ee055d and the kernel_config_sos present in the same

Jason/Fengwei, Our assumption is not correct. HV needs to handle RTL change even when it is unmasked. Anthony

Ok, it does one case that we don’t take care – the update is done during the interrupt is unmasked. Let’s figure out one solution for this. Thanks & Best Regards, Jason Chen SSG ->

This change update the interrupt from edge triggered to low level triggered. Which is unusual case. Is it possible that this is related with workaround in linux kernel ioapic for version

It happens because in the acpi table - DSDT - the interrupt is defined as level triggered active low for this device. Snippet from DSDT:Best Regards, Abdul

Hi, Fengwei, Just checked the ioapic workaround code, it will first do MASK before update. So I think it's not related with this IOAPIC workaround. Thanks & Best Regards, Jason Chen SSG -> OTC ->

Yes. It's not related with IOAPIC workaround. Here is what I got from SOS: ^M[ 0.041021] ioapic_set_affinity: yfw: eu.w1: 0x931, eu.w2: 0x1000000^M ^M[ 0.041085] ioapic_set_affinity: yfw:

During the second update function "acpi_create_platform_device" calls "acpi_dev_get_resources" which reads the acpi resources and updates the trigger mode and polarity of the interrupt. Best

Hello All, I would like to run ACRN on the MinnowBoard Turbot QUAD Core Board which has the Intel Atom® Processor E3845. I understand that this target is not tested, but I am up for the

Hi Joel, Welcome to try it on MinnowBoard and any patches are welcome! If you need any help, please send it to the mail list, we will answer your questions.

Hi there, I got an Aaeon’s AI Core, which integrates the Movidius Myriad2 chip and a USB3 controller on a PCIe card, and I’d like to drive it from the UOS on the UP2 board. I follow theGetting

Tonny, Could you pls. paste the detailed error mesg. We do have some passthrough rules user need follow, e.g. have reset capability for PCIe dev... On 2018/7/30 9:07,

Hi Edwin, Thanks for asking, here are my setup: - HV/DM: f815415 - SOS: Clear 24030 w/ 4.14.57-69 kernel - List of PCI devices ... 00:1f.0 ISA bridge: Intel Corporation Celeron N3350/Pentium

Tonny, The config is ok. Could you pls. try gdb to catch the seg fault? Just replace the 'acrn-dm' with 'gdb --args acrn-dm...' in your launch script. Did you paste all your