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Re: Support for NVMe drives in ACRN
Do u check the boot order in UEFI BIOS ? Generally, the boot order is under the control of BIOS. UEFI bios should have a watchdog timer, if the first boot item didn't call exit-boot-service, BIOS
Do u check the boot order in UEFI BIOS ? Generally, the boot order is under the control of BIOS. UEFI bios should have a watchdog timer, if the first boot item didn't call exit-boot-service, BIOS
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By
Chaohong guo <chaohong.guo@...>
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#52
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Re: Support for NVMe drives in ACRN
We haven't tried such combination before, will have a try and reply later.
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
Mail: hongbo.wang@...
We haven't tried such combination before, will have a try and reply later.
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
Mail: hongbo.wang@...
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By
Wang, Hongbo
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#51
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Support for NVMe drives in ACRN
Hi folks,
I have a NUC7i7BNH [1] that is equipped with both a NVMe and SATA SSD drive. I have Clear Linux 25130 installed on the SSD (SATA). There are a number of partitions on the NVMe drive but I'm
Hi folks,
I have a NUC7i7BNH [1] that is equipped with both a NVMe and SATA SSD drive. I have Clear Linux 25130 installed on the SSD (SATA). There are a number of partitions on the NVMe drive but I'm
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By
Geoffroy Van Cutsem
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#50
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[Announce] ACRN ver0.2 Release Notes
Hi all,
We are pleased to announceversion 0.2 release of ACRN. You can see the Release Notes in the website https://projectacrn.github.io/latest/release_notes.html.
To learn more about ACRN:
Hi all,
We are pleased to announceversion 0.2 release of ACRN. You can see the Release Notes in the website https://projectacrn.github.io/latest/release_notes.html.
To learn more about ACRN:
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By
Wang, Hongbo
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#49
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ACRN Project Technical Community Meeting: @ Weekly 9PM-10PM (China-Shanghai), 6AM-7AM (US-West Coast), 3PM-4PM (Europe-London)
Agenda of 9/26: USB Virtualizationin ACRN
Description: Not like server virtualization, devices virtualization is one of features for ACRN’s sharing mode usage. In this talk, presenter will introduce
Agenda of 9/26: USB Virtualizationin ACRN
Description: Not like server virtualization, devices virtualization is one of features for ACRN’s sharing mode usage. In this talk, presenter will introduce
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By
Wang, Hongbo
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#48
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Re: ACRN support on UP2
Hi,
By
Marathe, Yogesh
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#47
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Re: ACRN support on UP2
Hi Yogesh,
By
Geoffroy Van Cutsem
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#46
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Re: ACRN support on UP2
Hi Auke,
By
Marathe, Yogesh
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#45
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Re: ACRN support on UP2
It should, because that is what it is being tested on - APL NUCs
https://ark.intel.com/products/95594/Intel-Celeron-Processor-J3455-2M-Cache-up-to-2_3-GHz
4 cores, no HT support.
Auke
It should, because that is what it is being tested on - APL NUCs
https://ark.intel.com/products/95594/Intel-Celeron-Processor-J3455-2M-Cache-up-to-2_3-GHz
4 cores, no HT support.
Auke
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By
auke-jan.h.kok@...
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#44
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ACRN support on UP2
Hello,
I see there are 3 variants of SOC in UP2datasheet (Celeron, Pentium and Atom). Does ACRN support Atom version? If no, is there any plan to support Atom?
On ACRN website, it mentions
Hello,
I see there are 3 variants of SOC in UP2datasheet (Celeron, Pentium and Atom). Does ACRN support Atom version? If no, is there any plan to support Atom?
On ACRN website, it mentions
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By
Marathe, Yogesh
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#43
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ACRN Project Technical Community Meeting Miutes - 9/19/2018
Minutes Achieve: https://docs.google.com/document/d/1VSAbg33qcF3Ee0kQ4MWjcN4YRwpGUWpakqA0IWVGtwQ/edit#
ACRN Project TCM - 19th September 2018
Location
Online conference link:
Minutes Achieve: https://docs.google.com/document/d/1VSAbg33qcF3Ee0kQ4MWjcN4YRwpGUWpakqA0IWVGtwQ/edit#
ACRN Project TCM - 19th September 2018
Location
Online conference link:
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By
Wang, Hongbo
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#42
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FYI: Slim Boot Loader has Launched!
FYI.
SBL was announced as the OpenSource FW Conference 2018 in Erlangen, Germany. If you go to the github link athttps://github.com/slimbootloaderyou can find the source code and associated
FYI.
SBL was announced as the OpenSource FW Conference 2018 in Erlangen, Germany. If you go to the github link athttps://github.com/slimbootloaderyou can find the source code and associated
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By
Wang, Hongbo
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#41
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Re: How to pass through off-chip USB controller
Thanks Binbin!
By
Geoffroy Van Cutsem
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#40
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Re: How to pass through off-chip USB controller
Hi Geoffroy,
Yes, and the PR has been sent out.
https://github.com/projectacrn/acrn-hypervisor/pull/1210
Hi Geoffroy,
Yes, and the PR has been sent out.
https://github.com/projectacrn/acrn-hypervisor/pull/1210
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By
Wu, Binbin
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#39
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Re: How to pass through off-chip USB controller
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Geoffroy Van Cutsem
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#38
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Re: How to pass through off-chip USB controller
Hi Geoffroy,
Thanks for providing the info.
After checking the code, I did found a logic error when handling msix table read/write in passthrough.
I have sent out a patch to fix the issue to
Hi Geoffroy,
Thanks for providing the info.
After checking the code, I did found a logic error when handling msix table read/write in passthrough.
I have sent out a patch to fix the issue to
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By
Wu, Binbin
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#37
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Re: How to pass through off-chip USB controller
Hi Binbin, Edwin,
The error Tonny got at the time was with this combination (so not the latest as of today):
- HV/DM: f815415
- SOS: Clear 24030 w/ 4.14.57-69 kernel
Looking it up on Github,
Hi Binbin, Edwin,
The error Tonny got at the time was with this combination (so not the latest as of today):
- HV/DM: f815415
- SOS: Clear 24030 w/ 4.14.57-69 kernel
Looking it up on Github,
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By
Geoffroy Van Cutsem
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#36
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Re: How to pass through off-chip USB controller
Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether hw/pci/passthrough.c:560 is the line of code in bold?
static void
msix_table_write(struct vmctx
Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether hw/pci/passthrough.c:560 is the line of code in bold?
static void
msix_table_write(struct vmctx
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By
Wu, Binbin
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#35
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Re: How to pass through off-chip USB controller
Geoffroy,
Sorry, I seemed miss Tonny's reply.
From the lspci output from him, this controller support MSI-x, which probably trigger potential issue in ACRN side.
Geoffroy,
Sorry, I seemed miss Tonny's reply.
From the lspci output from him, this controller support MSI-x, which probably trigger potential issue in ACRN side.
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By
Zhai, Edwin <edwin.zhai@...>
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#34
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Re: How to pass through off-chip USB controller
Ops, hit "send" by mistake earlier
Thanks for jumping in! I think Tonny (who initiated this thread) was further than that. Edwin had indicated the error came from an MSIx access error and had asked
Ops, hit "send" by mistake earlier
Thanks for jumping in! I think Tonny (who initiated this thread) was further than that. Edwin had indicated the error came from an MSIx access error and had asked
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By
Geoffroy Van Cutsem
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#33
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