I don’t meet that issue. If you have Pre-launched RTVM / Service VM, you can check in ACRN console: vm_list And then vm_console N to switch the VM console. Thanks Minggui

Yes, it is for L3 CAT. You can check tgl-rvp.xml the board file, there are some changes for L3 info. Current, ACRN just supports one of L2/L3 CAT, if you need support both, you can do it as hard

IT WORKS! I set the scenario as you said and now I can read the cache events. Thank you so much for the help. Only one small note: when I use the GUEST_FLAG_LAPIC_PASSTHROUGH flag, the terminal of the

Hi Minggui, Do you mean that for L3 CAT setting, i also need specify it in the board xmls in the CLOS info portion? if i want to use both L2 and L3 CAT, how would i definte that in the board xmls?

Hi, for CAT support (L2/L3), you can check it by cpuid; For L2, if on core platform it is private for a physical core, L3/LLC is shared between cores, if hyper-threading is not enabled, L2 CAT

That is reasonable. It means APIC pass-through not set. Let me check, You can refer this file to modify yours: misc/config_tools/data/whl-ipc-i5/hybrid_rt.xml <vm id="0">

Hi ACRN experts, based on this guide https://projectacrn.github.io/latest/tutorials/rdt_configuration.html#configure-rdt-for-vm-using-vm-configuration I see that L2 cache is enabled for CAT but i'm

Hi Minggui, I'm sorry, I didn't realize I had to read the 0x186 register from inside the VM. I had read it from the ACRN shell (ACRN: \> rdmsr 0x186). Actually, I cannot read these registers from the

Hi, Paolo, Could you check again to rdmsr 0x186 and 0x38f? If the ACRN has not pass-through PMU to VM, it shall like following: root@10239146109sos-dom0:~# dmesg | grep -i pmu [

noted, would this be implemented in the future? i don't have a use case for this, just want to double confirm my changes on scenario xml in the target board itself

Hi Minggui, I checked "dmesg | grep -i pmu" and it returned me: [ 0.075539] Performance Events: unsupported p6 CPU model 150 no PMU driver, software events only. And all the events in your perf

Following is an example from my side: ./perf stat -C 1 -e mem_load_retired.l2_hit,mem_load_retired.l2_miss,mem_load_retired.l3_hit,mem_load_retired.l3_miss ./pmu_mem -a 1 -p 80 -l 1 -m 12

Hi, Paolo, If you can read 0x186, it means, you can read PMU MSRs, it shall work for perf to sample some events, like LLC misses. You can also check by: dmesg | grep -i pmu To

Scenario files:

Hi Minggui, Thanks for the quick answer. With my original scenario, I tried rdmsr 0x186 and it returned rdmsr(0x186):0x0. Is it ok? Then I modified the scenario and i get a lot of errors: First I

I do not believe this is possible although this may be an interesting feature. What use-case do you have in mind for this? Geoffroy

Hi ACRN experts, Is there a way for me to extract my scenario xmls information from the hypervisor binary or from the target itself rather than from the acrn hypervisor build folder?

Hi，Paolo, In ACRN2.7 it has supported to pass-through PMU (hardware events) to RTVM. For cache-misses, LLC-stores, LLC-store-misses hardware events, it shall support. You can have a check

Hi everyone, I am working with ACRN in order to make some performance test on VMs in a pre-launched scenario. To take measurements i thought to use perf but it seems there is no way to access the

ACRN Project TCM - 16th Mar 2022 Location Online by Zoom: https://zoom.com.cn/j/320664063 Attendees (Total 10, 16/03) Agenda ACRN project update: Celebrating 4th Birthday, Project ACRN™: