Date   

Re: ACRN on CoffeeLake

Victor Sun
 

Hi Rajagopal,


Please post your UOS launch script.


BR,

Victor


On 11/21/2019 1:41 PM, Rajagopal Aravindan via Lists.Projectacrn.Org wrote:

Hello Victor,

W.r.t the subject, we were able to get ACRN to boot into SOS.
However, when trying  to start UOS we run into the below error

GVT: open /sys/kernel/gvt/control/create_gvt_instance failed
GVT: init failed
: No such file or directory
pci pci-gvt init failed

I guess its related to graphics virtualization but not able to get past that.

Any inputs on this, please ?

PFB (my signature) the board & sdc xmls.

Thanks,
Rajagopal

board.xml
<acrn-config board="acer">
	<BIOS_INFO>
	BIOS Information
	Vendor: Acer
	Version: P21-A1E
	Release Date: 04/12/2019
	BIOS Revision: 5.12
	</BIOS_INFO>

	<BASE_BOARD_INFO>
	Base Board Information
	Manufacturer: Acer
	Product Name: H310CH5-M23
	Version: P21-A1E
	</BASE_BOARD_INFO>

	<PCI_DEVICE>
	00:00.0 Host bridge: Intel Corporation 8th Gen Core Processor Host Bridge/DRAM Registers (rev 08)
	00:02.0 VGA compatible controller: Intel Corporation 8th Gen Core Processor Gaussian Mixture Model
	Region 0: Memory at de000000 (64-bit, non-prefetchable) [size=16M]
	Region 2: Memory at c0000000 (64-bit, prefetchable) [size=256M]
	00:08.0 System peripheral: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th Gen Core Processor Gaussian Mixture Model
	Region 0: Memory at df12f000 (64-bit, non-prefetchable) [disabled] [size=4K]
	00:14.0 USB controller: Intel Corporation 200 Series/Z370 Chipset Family USB 3.0 xHCI Controller
	Region 0: Memory at df110000 (64-bit, non-prefetchable) [size=64K]
	00:14.2 Signal processing controller: Intel Corporation 200 Series PCH Thermal Subsystem
	Region 0: Memory at df12e000 (64-bit, non-prefetchable) [size=4K]
	00:16.0 Communication controller: Intel Corporation 200 Series PCH CSME HECI #1
	Region 0: Memory at df12d000 (64-bit, non-prefetchable) [size=4K]
	00:17.0 SATA controller: Intel Corporation 200 Series PCH SATA controller [AHCI mode]
	Region 0: Memory at df128000 (32-bit, non-prefetchable) [size=8K]
	Region 1: Memory at df12c000 (32-bit, non-prefetchable) [size=256]
	Region 5: Memory at df12b000 (32-bit, non-prefetchable) [size=2K]
	00:1c.0 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5 (rev f0)
	00:1f.0 ISA bridge: Intel Corporation Device a2ca
	00:1f.2 Memory controller: Intel Corporation 200 Series/Z370 Chipset Family Power Management Controller
	Region 0: Memory at df124000 (32-bit, non-prefetchable) [disabled] [size=16K]
	00:1f.3 Audio device: Intel Corporation 200 Series PCH HD Audio
	Region 0: Memory at df120000 (64-bit, non-prefetchable) [size=16K]
	Region 4: Memory at df100000 (64-bit, non-prefetchable) [size=64K]
	00:1f.4 SMBus: Intel Corporation 200 Series/Z370 Chipset Family SMBus Controller
	Region 0: Memory at df12a000 (64-bit, non-prefetchable) [size=256]
	01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)
	Region 2: Memory at df004000 (64-bit, non-prefetchable) [size=4K]
	Region 4: Memory at df000000 (64-bit, non-prefetchable) [size=16K]
	</PCI_DEVICE>

	<PCI_VID_PID>
	00:00.0 0600: 8086:3e1f (rev 08)
	00:02.0 0300: 8086:3e91
	00:08.0 0880: 8086:1911
	00:14.0 0c03: 8086:a2af
	00:14.2 1180: 8086:a2b1
	00:16.0 0780: 8086:a2ba
	00:17.0 0106: 8086:a282
	00:1c.0 0604: 8086:a294 (rev f0)
	00:1f.0 0601: 8086:a2ca
	00:1f.2 0580: 8086:a2a1
	00:1f.3 0403: 8086:a2f0
	00:1f.4 0c05: 8086:a2a3
	01:00.0 0200: 10ec:8168 (rev 15)
	</PCI_VID_PID>

	<WAKE_VECTOR_INFO>
	#define WAKE_VECTOR_32          0xB65B0F0CUL
	#define WAKE_VECTOR_64          0xB65B0F18UL
	</WAKE_VECTOR_INFO>

	<RESET_REGISTER_INFO>
	#define RESET_REGISTER_ADDRESS  0xCF9UL
	#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
	#define RESET_REGISTER_VALUE    0x6U
	</RESET_REGISTER_INFO>

	<PM_INFO>
	#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_EVT_BIT_WIDTH      0x20U
	#define PM1A_EVT_BIT_OFFSET     0x0U
	#define PM1A_EVT_ADDRESS        0x1800UL
	#define PM1A_EVT_ACCESS_SIZE    0x2U
	#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_EVT_BIT_WIDTH      0x0U
	#define PM1B_EVT_BIT_OFFSET     0x0U
	#define PM1B_EVT_ADDRESS        0x0UL
	#define PM1B_EVT_ACCESS_SIZE    0x2U
	#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_CNT_BIT_WIDTH      0x10U
	#define PM1A_CNT_BIT_OFFSET     0x0U
	#define PM1A_CNT_ADDRESS        0x1804UL
	#define PM1A_CNT_ACCESS_SIZE    0x2U
	#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_CNT_BIT_WIDTH      0x0U
	#define PM1B_CNT_BIT_OFFSET     0x0U
	#define PM1B_CNT_ADDRESS        0x0UL
	#define PM1B_CNT_ACCESS_SIZE    0x2U
	</PM_INFO>

	<S3_INFO>
	#define S3_PKG_VAL_PM1A         0x5U
	#define S3_PKG_VAL_PM1B         0U
	#define S3_PKG_RESERVED         0x0U
	</S3_INFO>

	<S5_INFO>
	#define S5_PKG_VAL_PM1A         0x7U
	#define S5_PKG_VAL_PM1B         0U
	#define S5_PKG_RESERVED         0x0U
	</S5_INFO>

	<DRHD_INFO>
	#define DRHD_COUNT              2U

	#define DRHD0_DEV_CNT           0x1U
	#define DRHD0_SEGMENT           0x0U
	#define DRHD0_FLAGS             0x0U
	#define DRHD0_REG_BASE          0xFED90000UL
	#define DRHD0_IGNORE            true
	#define DRHD0_DEVSCOPE0_TYPE    0x1U
	#define DRHD0_DEVSCOPE0_ID      0x0U
	#define DRHD0_DEVSCOPE0_BUS     0x0U
	#define DRHD0_DEVSCOPE0_PATH    0x10U

	#define DRHD1_DEV_CNT           0x2U
	#define DRHD1_SEGMENT           0x0U
	#define DRHD1_FLAGS             0x1U
	#define DRHD1_REG_BASE          0xFED91000UL
	#define DRHD1_IGNORE            false
	#define DRHD1_DEVSCOPE0_TYPE    0x3U
	#define DRHD1_DEVSCOPE0_ID      0x2U
	#define DRHD1_DEVSCOPE0_BUS     0xf0U
	#define DRHD1_DEVSCOPE0_PATH    0xf8U
	#define DRHD1_DEVSCOPE1_TYPE    0x4U
	#define DRHD1_DEVSCOPE1_ID      0x0U
	#define DRHD1_DEVSCOPE1_BUS     0x0U
	#define DRHD1_DEVSCOPE1_PATH    0xf8U

	</DRHD_INFO>

	<CPU_BRAND>
	"Intel(R) Core(TM) i3-8100 CPU @ 3.60GHz"
	</CPU_BRAND>

	<CX_INFO>
	{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U},	/* C1 */
	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x97U, 0x00U},	/* C2 */
	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U},	/* C3 */
	</CX_INFO>

	<PX_INFO>
	{0xE10UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002400UL, 0x002400UL},	/* P0 */
	{0xD48UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002200UL, 0x002200UL},	/* P1 */
	{0xC80UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002000UL, 0x002000UL},	/* P2 */
	{0xBB8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001E00UL, 0x001E00UL},	/* P3 */
	{0xB54UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001D00UL, 0x001D00UL},	/* P4 */
	{0xA8CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001B00UL, 0x001B00UL},	/* P5 */
	{0x9C4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001900UL, 0x001900UL},	/* P6 */
	{0x8FCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL},	/* P7 */
	{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL},	/* P8 */
	{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL},	/* P9 */
	{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL},	/* P10 */
	{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL},	/* P11 */
	{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL},	/* P12 */
	{0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL},	/* P13 */
	{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL},	/* P14 */
	{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL},	/* P15 */
	</PX_INFO>

	<CLOS_INFO>
	clos supported by cache:False
	clos max:0
	</CLOS_INFO>

	<SYSTEM_RAM_INFO>
	00001000-00057fff : System RAM
	00059000-0009dfff : System RAM
	00100000-3fffffff : System RAM
	40400000-ae6bafff : System RAM
	ae6bd000-b58b7fff : System RAM
	b6540000-b6549fff : System RAM
	b6ffe000-b6ffefff : System RAM
	100000000-23effffff : System RAM
	</SYSTEM_RAM_INFO>

	<BLOCK_DEVICE_INFO>
	/dev/sda3: TYPE="ext4"
	/dev/sda4: TYPE="ext4"
	</BLOCK_DEVICE_INFO>

	<TTYS_INFO>
	seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
	</TTYS_INFO>

	<AVAILABLE_IRQ_INFO>
	3, 5, 6, 7, 10, 11, 12, 13, 14, 15
	</AVAILABLE_IRQ_INFO>

	<TOTAL_MEM_INFO>
	7975552 kB
	</TOTAL_MEM_INFO>

	<CPU_PROCESSOR_INFO>
	0, 1, 2, 3
	</CPU_PROCESSOR_INFO>

</acrn-config>

sdc.xml
<?xml version='1.0' encoding='utf-8'?>
<acrn-config board="acer" scenario="sdc">
    <vm id="0">
        <load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">SOS_VM</load_order>
        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
        <uuid configurable="0" desc="vm uuid">dbbbd434-7a57-4216-a12c-2201f1ab0240</uuid>
        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
            <guest_flag>GUEST_FLAG_HIGHEST_SEVERITY</guest_flag>
        </guest_flags>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution." />
        <memory>
            <start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
            <size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
        </memory>
        <os_config>
            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
            <bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
        </os_config>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." readonly="true">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
        </vuart>
        <pci_dev_num configurable="0" desc="pci devices number">SOS_EMULATED_PCI_DEV_NUM</pci_dev_num>
        <pci_devs configurable="0" desc="pci devices list">sos_pci_devs</pci_devs>
        <board_private>
            <rootfs desc="rootfs for Linux kernel">/dev/sda3</rootfs>
            <console desc="ttyS console for Linux kernel">/dev/ttyS0</console>
            <bootargs desc="Specify kernel boot arguments">        rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
        i915.nuclear_pageflip=1 i915.avail_planes_per_pipe=0x01010F i915.domain_plane_owners=0x011111110000 i915.enable_gvt=1
        </bootargs>
        </board_private>
    </vm>
    <vm id="1">
        <load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">POST_LAUNCHED_VM</load_order>
        <uuid configurable="0" desc="vm uuid">d2795438-25d6-11e8-864e-cb7a18b34643</uuid>
        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
            <guest_flag />
        </guest_flags>
        <vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
            <pcpu_id>1</pcpu_id>
            <pcpu_id>2</pcpu_id>
            <pcpu_id>3</pcpu_id>
        </vcpu_affinity>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution." />
        <epc_section desc="epc section">
            <base desc="SGX EPC section base, must be page aligned">0</base>
            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
        </epc_section>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." >INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base> 
            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
        </vuart>
    </vm>
    <vm configurable="0" desc="specific for Kata" id="2">
        <load_order configurable="0" desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM.">POST_LAUNCHED_VM</load_order>
        <uuid configurable="0" desc="vm uuid">a7ada506-1ab0-4b6b-a0da-e513ca9b8c2f</uuid>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
        <vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
            <pcpu_id>3</pcpu_id>
        </vcpu_affinity>
        <epc_section desc="epc section">
            <base desc="SGX EPC section base, must be page aligned">0</base>
            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
        </epc_section>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base configurable="0" desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">COM1_BASE</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base configurable="0" desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM2 irq">COM2_BASE</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
        </vuart>
    </vm>
</acrn-config>
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ACRN on CoffeeLake

Rajagopal Aravindan
 

Hello Victor,

W.r.t the subject, we were able to get ACRN to boot into SOS.
However, when trying  to start UOS we run into the below error

GVT: open /sys/kernel/gvt/control/create_gvt_instance failed
GVT: init failed
: No such file or directory
pci pci-gvt init failed

I guess its related to graphics virtualization but not able to get past that.

Any inputs on this, please ?

PFB (my signature) the board & sdc xmls.

Thanks,
Rajagopal

board.xml
<acrn-config board="acer">
	<BIOS_INFO>
	BIOS Information
	Vendor: Acer
	Version: P21-A1E
	Release Date: 04/12/2019
	BIOS Revision: 5.12
	</BIOS_INFO>

	<BASE_BOARD_INFO>
	Base Board Information
	Manufacturer: Acer
	Product Name: H310CH5-M23
	Version: P21-A1E
	</BASE_BOARD_INFO>

	<PCI_DEVICE>
	00:00.0 Host bridge: Intel Corporation 8th Gen Core Processor Host Bridge/DRAM Registers (rev 08)
	00:02.0 VGA compatible controller: Intel Corporation 8th Gen Core Processor Gaussian Mixture Model
	Region 0: Memory at de000000 (64-bit, non-prefetchable) [size=16M]
	Region 2: Memory at c0000000 (64-bit, prefetchable) [size=256M]
	00:08.0 System peripheral: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th Gen Core Processor Gaussian Mixture Model
	Region 0: Memory at df12f000 (64-bit, non-prefetchable) [disabled] [size=4K]
	00:14.0 USB controller: Intel Corporation 200 Series/Z370 Chipset Family USB 3.0 xHCI Controller
	Region 0: Memory at df110000 (64-bit, non-prefetchable) [size=64K]
	00:14.2 Signal processing controller: Intel Corporation 200 Series PCH Thermal Subsystem
	Region 0: Memory at df12e000 (64-bit, non-prefetchable) [size=4K]
	00:16.0 Communication controller: Intel Corporation 200 Series PCH CSME HECI #1
	Region 0: Memory at df12d000 (64-bit, non-prefetchable) [size=4K]
	00:17.0 SATA controller: Intel Corporation 200 Series PCH SATA controller [AHCI mode]
	Region 0: Memory at df128000 (32-bit, non-prefetchable) [size=8K]
	Region 1: Memory at df12c000 (32-bit, non-prefetchable) [size=256]
	Region 5: Memory at df12b000 (32-bit, non-prefetchable) [size=2K]
	00:1c.0 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5 (rev f0)
	00:1f.0 ISA bridge: Intel Corporation Device a2ca
	00:1f.2 Memory controller: Intel Corporation 200 Series/Z370 Chipset Family Power Management Controller
	Region 0: Memory at df124000 (32-bit, non-prefetchable) [disabled] [size=16K]
	00:1f.3 Audio device: Intel Corporation 200 Series PCH HD Audio
	Region 0: Memory at df120000 (64-bit, non-prefetchable) [size=16K]
	Region 4: Memory at df100000 (64-bit, non-prefetchable) [size=64K]
	00:1f.4 SMBus: Intel Corporation 200 Series/Z370 Chipset Family SMBus Controller
	Region 0: Memory at df12a000 (64-bit, non-prefetchable) [size=256]
	01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)
	Region 2: Memory at df004000 (64-bit, non-prefetchable) [size=4K]
	Region 4: Memory at df000000 (64-bit, non-prefetchable) [size=16K]
	</PCI_DEVICE>

	<PCI_VID_PID>
	00:00.0 0600: 8086:3e1f (rev 08)
	00:02.0 0300: 8086:3e91
	00:08.0 0880: 8086:1911
	00:14.0 0c03: 8086:a2af
	00:14.2 1180: 8086:a2b1
	00:16.0 0780: 8086:a2ba
	00:17.0 0106: 8086:a282
	00:1c.0 0604: 8086:a294 (rev f0)
	00:1f.0 0601: 8086:a2ca
	00:1f.2 0580: 8086:a2a1
	00:1f.3 0403: 8086:a2f0
	00:1f.4 0c05: 8086:a2a3
	01:00.0 0200: 10ec:8168 (rev 15)
	</PCI_VID_PID>

	<WAKE_VECTOR_INFO>
	#define WAKE_VECTOR_32          0xB65B0F0CUL
	#define WAKE_VECTOR_64          0xB65B0F18UL
	</WAKE_VECTOR_INFO>

	<RESET_REGISTER_INFO>
	#define RESET_REGISTER_ADDRESS  0xCF9UL
	#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
	#define RESET_REGISTER_VALUE    0x6U
	</RESET_REGISTER_INFO>

	<PM_INFO>
	#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_EVT_BIT_WIDTH      0x20U
	#define PM1A_EVT_BIT_OFFSET     0x0U
	#define PM1A_EVT_ADDRESS        0x1800UL
	#define PM1A_EVT_ACCESS_SIZE    0x2U
	#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_EVT_BIT_WIDTH      0x0U
	#define PM1B_EVT_BIT_OFFSET     0x0U
	#define PM1B_EVT_ADDRESS        0x0UL
	#define PM1B_EVT_ACCESS_SIZE    0x2U
	#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_CNT_BIT_WIDTH      0x10U
	#define PM1A_CNT_BIT_OFFSET     0x0U
	#define PM1A_CNT_ADDRESS        0x1804UL
	#define PM1A_CNT_ACCESS_SIZE    0x2U
	#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_CNT_BIT_WIDTH      0x0U
	#define PM1B_CNT_BIT_OFFSET     0x0U
	#define PM1B_CNT_ADDRESS        0x0UL
	#define PM1B_CNT_ACCESS_SIZE    0x2U
	</PM_INFO>

	<S3_INFO>
	#define S3_PKG_VAL_PM1A         0x5U
	#define S3_PKG_VAL_PM1B         0U
	#define S3_PKG_RESERVED         0x0U
	</S3_INFO>

	<S5_INFO>
	#define S5_PKG_VAL_PM1A         0x7U
	#define S5_PKG_VAL_PM1B         0U
	#define S5_PKG_RESERVED         0x0U
	</S5_INFO>

	<DRHD_INFO>
	#define DRHD_COUNT              2U

	#define DRHD0_DEV_CNT           0x1U
	#define DRHD0_SEGMENT           0x0U
	#define DRHD0_FLAGS             0x0U
	#define DRHD0_REG_BASE          0xFED90000UL
	#define DRHD0_IGNORE            true
	#define DRHD0_DEVSCOPE0_TYPE    0x1U
	#define DRHD0_DEVSCOPE0_ID      0x0U
	#define DRHD0_DEVSCOPE0_BUS     0x0U
	#define DRHD0_DEVSCOPE0_PATH    0x10U

	#define DRHD1_DEV_CNT           0x2U
	#define DRHD1_SEGMENT           0x0U
	#define DRHD1_FLAGS             0x1U
	#define DRHD1_REG_BASE          0xFED91000UL
	#define DRHD1_IGNORE            false
	#define DRHD1_DEVSCOPE0_TYPE    0x3U
	#define DRHD1_DEVSCOPE0_ID      0x2U
	#define DRHD1_DEVSCOPE0_BUS     0xf0U
	#define DRHD1_DEVSCOPE0_PATH    0xf8U
	#define DRHD1_DEVSCOPE1_TYPE    0x4U
	#define DRHD1_DEVSCOPE1_ID      0x0U
	#define DRHD1_DEVSCOPE1_BUS     0x0U
	#define DRHD1_DEVSCOPE1_PATH    0xf8U

	</DRHD_INFO>

	<CPU_BRAND>
	"Intel(R) Core(TM) i3-8100 CPU @ 3.60GHz"
	</CPU_BRAND>

	<CX_INFO>
	{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U},	/* C1 */
	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x97U, 0x00U},	/* C2 */
	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U},	/* C3 */
	</CX_INFO>

	<PX_INFO>
	{0xE10UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002400UL, 0x002400UL},	/* P0 */
	{0xD48UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002200UL, 0x002200UL},	/* P1 */
	{0xC80UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002000UL, 0x002000UL},	/* P2 */
	{0xBB8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001E00UL, 0x001E00UL},	/* P3 */
	{0xB54UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001D00UL, 0x001D00UL},	/* P4 */
	{0xA8CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001B00UL, 0x001B00UL},	/* P5 */
	{0x9C4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001900UL, 0x001900UL},	/* P6 */
	{0x8FCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL},	/* P7 */
	{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL},	/* P8 */
	{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL},	/* P9 */
	{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL},	/* P10 */
	{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL},	/* P11 */
	{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL},	/* P12 */
	{0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL},	/* P13 */
	{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL},	/* P14 */
	{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL},	/* P15 */
	</PX_INFO>

	<CLOS_INFO>
	clos supported by cache:False
	clos max:0
	</CLOS_INFO>

	<SYSTEM_RAM_INFO>
	00001000-00057fff : System RAM
	00059000-0009dfff : System RAM
	00100000-3fffffff : System RAM
	40400000-ae6bafff : System RAM
	ae6bd000-b58b7fff : System RAM
	b6540000-b6549fff : System RAM
	b6ffe000-b6ffefff : System RAM
	100000000-23effffff : System RAM
	</SYSTEM_RAM_INFO>

	<BLOCK_DEVICE_INFO>
	/dev/sda3: TYPE="ext4"
	/dev/sda4: TYPE="ext4"
	</BLOCK_DEVICE_INFO>

	<TTYS_INFO>
	seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
	</TTYS_INFO>

	<AVAILABLE_IRQ_INFO>
	3, 5, 6, 7, 10, 11, 12, 13, 14, 15
	</AVAILABLE_IRQ_INFO>

	<TOTAL_MEM_INFO>
	7975552 kB
	</TOTAL_MEM_INFO>

	<CPU_PROCESSOR_INFO>
	0, 1, 2, 3
	</CPU_PROCESSOR_INFO>

</acrn-config>

sdc.xml
<?xml version='1.0' encoding='utf-8'?>
<acrn-config board="acer" scenario="sdc">
    <vm id="0">
        <load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">SOS_VM</load_order>
        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
        <uuid configurable="0" desc="vm uuid">dbbbd434-7a57-4216-a12c-2201f1ab0240</uuid>
        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
            <guest_flag>GUEST_FLAG_HIGHEST_SEVERITY</guest_flag>
        </guest_flags>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution." />
        <memory>
            <start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
            <size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
        </memory>
        <os_config>
            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
            <bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
        </os_config>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." readonly="true">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
        </vuart>
        <pci_dev_num configurable="0" desc="pci devices number">SOS_EMULATED_PCI_DEV_NUM</pci_dev_num>
        <pci_devs configurable="0" desc="pci devices list">sos_pci_devs</pci_devs>
        <board_private>
            <rootfs desc="rootfs for Linux kernel">/dev/sda3</rootfs>
            <console desc="ttyS console for Linux kernel">/dev/ttyS0</console>
            <bootargs desc="Specify kernel boot arguments">        rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
        i915.nuclear_pageflip=1 i915.avail_planes_per_pipe=0x01010F i915.domain_plane_owners=0x011111110000 i915.enable_gvt=1
        </bootargs>
        </board_private>
    </vm>
    <vm id="1">
        <load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">POST_LAUNCHED_VM</load_order>
        <uuid configurable="0" desc="vm uuid">d2795438-25d6-11e8-864e-cb7a18b34643</uuid>
        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
            <guest_flag />
        </guest_flags>
        <vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
            <pcpu_id>1</pcpu_id>
            <pcpu_id>2</pcpu_id>
            <pcpu_id>3</pcpu_id>
        </vcpu_affinity>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution." />
        <epc_section desc="epc section">
            <base desc="SGX EPC section base, must be page aligned">0</base>
            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
        </epc_section>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." >INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base> 
            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
        </vuart>
    </vm>
    <vm configurable="0" desc="specific for Kata" id="2">
        <load_order configurable="0" desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM.">POST_LAUNCHED_VM</load_order>
        <uuid configurable="0" desc="vm uuid">a7ada506-1ab0-4b6b-a0da-e513ca9b8c2f</uuid>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
        <vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
            <pcpu_id>3</pcpu_id>
        </vcpu_affinity>
        <epc_section desc="epc section">
            <base desc="SGX EPC section base, must be page aligned">0</base>
            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
        </epc_section>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base configurable="0" desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">COM1_BASE</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base configurable="0" desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM2 irq">COM2_BASE</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
        </vuart>
    </vm>
</acrn-config>
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ACRN Project Technical Community Meeting Minutes - 11/20/2019

Wang, Hongbo
 

 
ACRN Project TCM - 20th Nov 2019
Location
Agenda
  1. ACRN project update 
 
  1. “How to Enable ACRN on New Hardware Board” by SUN, Victor/ZHENG, Shuang
Download foil from ACRN Presentation->ACRN_TCM->WW47’19
Short description: When user wants to enable ACRN hypervisor on a new hardware board, where should they start? Previously we could only manually modify acrn-hypervisor source code and Guest VM launch script to boot Service VM and launch Guest VMs, which requires user be familiar with ACRN source code and Guest VM launch scripts. In this talk, we’ll introduce an acrn-config toolset to end users. The tool includes a webUI for user to configure the Board/Scenario/Launch configurations and make the build automatically. With acrn-config tool, users could save time to enable ACRN on their new board. 
 
  1. All: Community open discussion.
 
  1. Next meeting agenda proposal:
 
WW Topic Presenter Status
WW02 TPM2.0 virtualization in ACRN DENG, Wei 1/9
WW03 Polling mode Virtio and its advantage for RT VM DENG, Jie 1/16
WW04 Buffer sharing from UOS to SOS, HyperDMA usage LIU, Xinyun 1/23
WW05 USB HUB Virtualization WU, Xiaoguang 1/30
WW07 ACRN Device Model QoS Design LIU, Long 2/13
WW08 ACRN Debug Tips CHEN, Jason 2/20
WW09 GVT-g debug trace tool GONG, Zhipeng 2/27
WW10 Kata Container Architecture: First Steps with ACRN Dhanraj, Vijay  3/6
WW11 One ACRN hypervisor to support multi-platform WU, Xiangyang 3/13
WW12 Power button key mediator design in ACRN LIU, Yuan 3/20
WW13 Local APIC Virtualization Enhancement for Intel KBL platform LI, Fei 3/27
WW14 Safety VM Support YIN, FengWei 4/3
WW15 How to customize GPIO in ACRN LIU, Yuan 4/10
WW16 ACRN Cache QoS support based on CAT TAO, Yuhong 4/17
WW17 ACRN Real-Time measurement Methodology LI, Wilson 4/24
WW19 I2C Virtualization CHEN, Conghui 5/8
WW20 SGX Virtualization in ACRN WU, Binbin 5/15
WW21 Logger Improvement on acrn-dm CAO, Minggui 5/22
WW22 AcrnGT Virtual Display Deep Dive HE, Min 5/29
WW23 Local APIC Emulation and Pass-through Grandhi, Sainath 6/5
WW25
 
ACRN Functional Safety: Understanding and Mitigating Inter-VM Interference MAO, Junjie 6/19
WW26 Enable VwWorks as RTVM on ACRN FU, Kaige 6/26
WW27 ACRN 2.0 New Architecture Sharing - 1/2 REN, Jack 7/3
WW28 ACRN 2.0 New Architecture Sharing- 2/2 REN, Jack 7/10
WW29 How to enable open vSwitch on ACRN LIU, Yuan 7/17
WW30 ACRN Configuration Design Tool SUN, Victor 7/24
WW31 Design of GOP Driver for GVT-g HE, Min 7/31
WW32 Restricting Dynamic Resources from functional safety perspective MAO, Junjie 8/7
WW33 Android Virtual Secure Boot and key enrollment QI, Yadong/Zhao Shirley 8/14
WW34 Split ACRN’s Device Model CHEN, Jason CJ 8/21
WW35 ACRN Continuous Integration System Introduction ZHANG, Wenling 8/28
WW36 BKC for ACRN RT and vmexit analysis YAN, Like 9/4
WW37 ACRN Windows As A Guest (WaaG) Overview WANG, Yu1 9/11
WW38 ACRN Fuzzing Test HUANG, Yonghua 9/18
WW39 Implementation of GOP driver with AcrnGT LIU, Xinyun 9/25
WW41 Banish the Dead: Identifying and Removing Dead Code for Functional Safety MAO, Junjie 10/9
WW42 ACRN Memory Bandwidth Allocation (MBA) Dhanraj, Vijay 10/16
WW43 Enable OVMF for Service VM Wang, Qian 10/23
WW44 Windows As A Guest and HLK Introduction SHEN, Fangfang 10/29
WW45 Performance Monitoring Unit Introduction WU, Binbin 11/6
WW46 ACRN Schedule Framework Introduction LIU, Shuo 11/13
WW47 How to Enable ACRN on New Hardware Board SUN, Victor/Zheng, Shuang 11/20
 
Marketing/Events
  1.  
Resources
  1. Project URL: 
  1. Portal: https://projectacrn.org   
  2. Source code: https://github.com/projectacrn   
  3. email: info@... 
  4. Technical Mailing list: acrn-dev@... 
  1. Recommended Hardware platform (reference):
  1. Apollo Lake (SoC) UP2 (with serial port): AAEON UPS-APLC2-A10-0232 
  2. Apollo Lake (SoC) NUC (without serial port): NUC6CAYHL (at least 8G memory)
  3. Kabylake (Core) NUC (with serial port): NUC7i5DNHE
 
=======================
 
 
 
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
 
 


ACRN Project Technical Community Meeting (2019/7~2019/12): @ Weekly Wednesday 11AM (China-Shanghai), Tuesday 7PM (US-West Coast), Wednesday 3AM (Europe-London)

Wang, Hongbo
 

Notice: Join ACRN’s TCM meeting with WebEx till Nov. 2019
Due to Zoom’s connection issue in PRC mainland recently, we have to use WebEx to replace Zoom for ACRN TCM meeting temporarily. We’ll monitor Zoom’s availability closely and switch back to Zoom as it comes back to normal. Sorry for the inconvenience!
Cisco WebEx: https://intel.webex.com/intel/j.php?MTID=md8485ef1ef04eeee01805a7cb323801b  (More details is at the bottom of the meeting request)
 
 
Date: 11/20
Topic:  How to Deploy ACRN on New Hardware Board
Description: When user wants to enable ACRN hypervisor on a new hardware board, where should they start? Previously we could only manually modify acrn-hypervisor source code and Guest VM launch script to boot Service VM and launch Guest VMs, which requires user be familiar with ACRN source code and Guest VM launch scripts. In this talk, we’ll introduce an acrn-config toolset to end users. The tool includes a webUI for user to configure the Board/Scenario/Launch configurations and make the build automatically. With acrn-config tool, users could save time to enable ACRN on their new board.
 
WW Topic Presenter Status
WW02 TPM2.0 virtualization in ACRN DENG, Wei 1/9
WW03 Polling mode Virtio and its advantage for RT VM DENG, Jie 1/16
WW04 Buffer sharing from UOS to SOS, HyperDMA usage LIU, Xinyun 1/23
WW05 USB HUB Virtualization WU, Xiaoguang 1/30
WW07 ACRN Device Model QoS Design LIU, Long 2/13
WW08 ACRN Debug Tips CHEN, Jason 2/20
WW09 GVT-g debug trace tool GONG, Zhipeng 2/27
WW10 Kata Container Architecture: First Steps with ACRN Dhanraj, Vijay  3/6
WW11 One ACRN hypervisor to support multi-platform WU, Xiangyang 3/13
WW12 Power button key mediator design in ACRN LIU, Yuan 3/20
WW13 Local APIC Virtualization Enhancement for Intel KBL platform LI, Fei 3/27
WW14 Safety VM Support YIN, FengWei 4/3
WW15 How to customize GPIO in ACRN LIU, Yuan 4/10
WW16 ACRN Cache QoS support based on CAT TAO, Yuhong 4/17
WW17 ACRN Real-Time measurement Methodology LI, Wilson 4/24
WW19 I2C Virtualization CHEN, Conghui 5/8
WW20 SGX Virtualization in ACRN WU, Binbin 5/15
WW21 Logger Improvement on acrn-dm CAO, Minggui 5/22
WW22 AcrnGT Virtual Display Deep Dive HE, Min 5/29
WW23 Local APIC Emulation and Pass-through Grandhi, Sainath 6/5
WW25
 
ACRN Functional Safety: Understanding and Mitigating Inter-VM Interference MAO, Junjie 6/19
WW26 Enable VwWorks as RTVM on ACRN FU, Kaige 6/26
WW27 ACRN 2.0 New Architecture Sharing - 1/2 REN, Jack 7/3
WW28 ACRN 2.0 New Architecture Sharing- 2/2 REN, Jack 7/10
WW29 How to enable open vSwitch on ACRN LIU, Yuan 7/17
WW30 ACRN Configuration Design Tool SUN, Victor 7/24
WW31 Design of GOP Driver for GVT-g HE, Min 7/31
WW32 On Dynamic Resource Allocation Mao, Junjie 8/7
WW33 ACRN virtual secure boot and key enrollment Wang, Kai 8/14
WW34 Split ACRN’s Device Model CHEN, Jason CJ 8/21
WW35 ACRN Continuous Integration System Introduction ZHANG, Wenling 8/28
WW36 BKC for ACRN RT and vmexit analysis YAN, Like 9/4
WW37 ACRN Windows As A Guest (WaaG) Overview CHEN, Jianjun 9/11
WW38 ACRN Fuzzing Test HUANG, Yonghua 9/18
WW39 Implementation of GOP driver with AcrnGT LIU, Xinyun 9/25
WW41 Banish the Dead: Identifying and Removing Dead Code for Functional Safety MAO, Junjie 10/9
WW42 ACRN Memory Bandwidth Allocation (MBA) Vijay Dhanraj 10/16
WW43 Enable OVMF for Service VM WANG, Qian 10/23
WW44 WaaG and Its HLK SHEN, Fangfang 10/30
WW45 Performance Monitoring Unit Introduction WU, Binbin 11/6
WW46 ACRN Schedule Framework Introduction LIU, Shuo 11/13
WW47 How to Deploy ACRN on New Hardware Board SUN, Victor 11/19
 
 
 
Project ACRN: A flexible, light-weight, open source reference hypervisor for IoT devices
 
We're still in the early stages of forming this TSC, so instead we invite you to attend a weekly "Technical Community" meeting where we'll meet community members and talk about the ACRN project and plans. As we explore community interest and involvement opportunities, we'll (re)schedule these meetings at a time convenient to most attendees:
  • -- Do not delete or change any of the following text. --  
  • When it's time, join your Webex meeting here.
 
 
Meeting number (access code): 590 576 334
Meeting password: ShFp3MC@ 
 
 
Join
 
 
 
 
Join by phone 
Tap to call in from a mobile device (attendees only) 
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Join from a video system or application
Dial 590576334@... 
You can also dial 173.243.2.68 and enter your meeting number.  
 
 
 
 
  • Meeting Notes:
 
 
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
 
 
 
 
 
 
 
 
 
 


Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Victor Sun
 

HI Rajagopal,

We reproduced the issue, the root cause is your board file has no <TTYS_INFO> settings. (i.e. no serial port/COMx device. )

We will deliver patch soon to bypass TTYS check. But as I mentioned before, without serial port ACRN will be very hard to debug issues.

BR,

Victor


On 11/18/2019 1:46 PM, Rajagopal Aravindan via Lists.Projectacrn.Org wrote:

Hello Victor,

>>Could you please share your board xml file?
PFB (my signature) the board xml.

Thanks,
Rajagopal

<acrn-config board="lenl450">
<BIOS_INFO>
BIOS Information
Vendor: LENOVO
Version: JDET55WW (1.17 )
Release Date: 11/20/2015
BIOS Revision: 1.17
</BIOS_INFO>

<BASE_BOARD_INFO>
Base Board Information
Manufacturer: LENOVO
Product Name: Intel powered classmate PC
Version: SDK0E50510 WIN
</BASE_BOARD_INFO>

<PCI_DEVICE>
00:00.0 Host bridge: Intel Corporation Broadwell-U Host Bridge -OPI (rev 09)
00:02.0 VGA compatible controller: Intel Corporation HD Graphics 5500 (rev 09)
Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at c0000000 (64-bit, prefetchable) [size=512M]
00:03.0 Audio device: Intel Corporation Broadwell-U Audio Controller (rev 09)
Region 0: Memory at e1230000 (64-bit, non-prefetchable) [size=16K]
00:14.0 USB controller: Intel Corporation Wildcat Point-LP USB xHCI Controller (rev 03)
Region 0: Memory at e1220000 (64-bit, non-prefetchable) [size=64K]
00:16.0 Communication controller: Intel Corporation Wildcat Point-LP MEI Controller #1 (rev 03)
Region 0: Memory at e1239000 (64-bit, non-prefetchable) [size=32]
00:19.0 Ethernet controller: Intel Corporation Ethernet Connection (3) I218-LM (rev 03)
Region 0: Memory at e1200000 (32-bit, non-prefetchable) [size=128K]
Region 1: Memory at e123e000 (32-bit, non-prefetchable) [size=4K]
00:1b.0 Audio device: Intel Corporation Wildcat Point-LP High Definition Audio Controller (rev 03)
Region 0: Memory at e1234000 (64-bit, non-prefetchable) [size=16K]
00:1c.0 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #1 (rev e3)
00:1c.2 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #3 (rev e3)
00:1c.5 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #6 (rev e3)
00:1d.0 USB controller: Intel Corporation Wildcat Point-LP USB EHCI Controller (rev 03)
Region 0: Memory at e123d000 (32-bit, non-prefetchable) [size=1K]
00:1f.0 ISA bridge: Intel Corporation Wildcat Point-LP LPC Controller (rev 03)
00:1f.2 SATA controller: Intel Corporation Wildcat Point-LP SATA Controller [AHCI Mode] (rev 03)
Region 5: Memory at e123c000 (32-bit, non-prefetchable) [size=2K]
00:1f.3 SMBus: Intel Corporation Wildcat Point-LP SMBus Controller (rev 03)
Region 0: Memory at e1238000 (64-bit, non-prefetchable) [size=256]
00:1f.6 Signal processing controller: Intel Corporation Wildcat Point-LP Thermal Management Controller (rev 03)
Region 0: Memory at e123b000 (64-bit, non-prefetchable) [size=4K]
04:00.0 Network controller: Intel Corporation Wireless 7265 (rev 61)
Region 0: Memory at e1100000 (64-bit, non-prefetchable) [size=8K]
05:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTS5227 PCI Express Card Reader (rev 01)
Region 0: Memory at e1000000 (32-bit, non-prefetchable) [size=4K]
</PCI_DEVICE>

<PCI_VID_PID>
00:00.0 0600: 8086:1604 (rev 09)
00:02.0 0300: 8086:1616 (rev 09)
00:03.0 0403: 8086:160c (rev 09)
00:14.0 0c03: 8086:9cb1 (rev 03)
00:16.0 0780: 8086:9cba (rev 03)
00:19.0 0200: 8086:15a2 (rev 03)
00:1b.0 0403: 8086:9ca0 (rev 03)
00:1c.0 0604: 8086:9c90 (rev e3)
00:1c.2 0604: 8086:9c94 (rev e3)
00:1c.5 0604: 8086:9c9a (rev e3)
00:1d.0 0c03: 8086:9ca6 (rev 03)
00:1f.0 0601: 8086:9cc3 (rev 03)
00:1f.2 0106: 8086:9c83 (rev 03)
00:1f.3 0c05: 8086:9ca2 (rev 03)
00:1f.6 1180: 8086:9ca4 (rev 03)
04:00.0 0280: 8086:095b (rev 61)
05:00.0 ff00: 10ec:5227 (rev 01)
</PCI_VID_PID>

<WAKE_VECTOR_INFO>
#define WAKE_VECTOR_32          0xACF6800CUL
#define WAKE_VECTOR_64          0xACF68018UL
</WAKE_VECTOR_INFO>

<RESET_REGISTER_INFO>
#define RESET_REGISTER_ADDRESS  0xCF9UL
#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
#define RESET_REGISTER_VALUE    0x6U
</RESET_REGISTER_INFO>

<PM_INFO>
#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1A_EVT_BIT_WIDTH      0x20U
#define PM1A_EVT_BIT_OFFSET     0x0U
#define PM1A_EVT_ADDRESS        0x1800UL
#define PM1A_EVT_ACCESS_SIZE    0x2U
#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1B_EVT_BIT_WIDTH      0x0U
#define PM1B_EVT_BIT_OFFSET     0x0U
#define PM1B_EVT_ADDRESS        0x0UL
#define PM1B_EVT_ACCESS_SIZE    0x2U
#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1A_CNT_BIT_WIDTH      0x10U
#define PM1A_CNT_BIT_OFFSET     0x0U
#define PM1A_CNT_ADDRESS        0x1804UL
#define PM1A_CNT_ACCESS_SIZE    0x2U
#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1B_CNT_BIT_WIDTH      0x0U
#define PM1B_CNT_BIT_OFFSET     0x0U
#define PM1B_CNT_ADDRESS        0x0UL
#define PM1B_CNT_ACCESS_SIZE    0x2U
</PM_INFO>

<S3_INFO>
</S3_INFO>

<S5_INFO>
</S5_INFO>

<DRHD_INFO>
#define DRHD_COUNT              2U

#define DRHD0_DEV_CNT           0x1U
#define DRHD0_SEGMENT           0x0U
#define DRHD0_FLAGS             0x0U
#define DRHD0_REG_BASE          0xFED90000UL
#define DRHD0_IGNORE            true
#define DRHD0_DEVSCOPE0_TYPE    0x1U
#define DRHD0_DEVSCOPE0_ID      0x0U
#define DRHD0_DEVSCOPE0_BUS     0x0U
#define DRHD0_DEVSCOPE0_PATH    0x10U

#define DRHD1_DEV_CNT           0x2U
#define DRHD1_SEGMENT           0x0U
#define DRHD1_FLAGS             0x1U
#define DRHD1_REG_BASE          0xFED91000UL
#define DRHD1_IGNORE            false
#define DRHD1_DEVSCOPE0_TYPE    0x3U
#define DRHD1_DEVSCOPE0_ID      0x2U
#define DRHD1_DEVSCOPE0_BUS     0xf0U
#define DRHD1_DEVSCOPE0_PATH    0xf8U
#define DRHD1_DEVSCOPE1_TYPE    0x4U
#define DRHD1_DEVSCOPE1_ID      0x0U
#define DRHD1_DEVSCOPE1_BUS     0xf0U
#define DRHD1_DEVSCOPE1_PATH    0x78U

</DRHD_INFO>

<CPU_BRAND>
"Intel(R) Core(TM) i5-5300U CPU @ 2.30GHz"
</CPU_BRAND>

<CX_INFO>
/* Cx data is not available */
</CX_INFO>

<PX_INFO>
{0x8FDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001D00UL, 0x001D00UL}, /* P0 */
{0x8FCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL}, /* P1 */
{0x898UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001600UL, 0x001600UL}, /* P2 */
{0x7D0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001400UL, 0x001400UL}, /* P3 */
{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P4 */
{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P5 */
{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P6 */
{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P7 */
{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P8 */
{0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */
{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P10 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P11 */
{0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P12 */
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P13 */
{0x258UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000600UL, 0x000600UL}, /* P14 */
{0x1F4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000500UL, 0x000500UL}, /* P15 */
</PX_INFO>

<CLOS_INFO>
clos supported by cache:False
clos max:0
</CLOS_INFO>

<TTYS_INFO>
</TTYS_INFO>

<SYSTEM_RAM_INFO>
00001000-00057fff : System RAM
00059000-0008bfff : System RAM
00100000-a9efdfff : System RAM
acfff000-acffffff : System RAM
100000000-24dffffff : System RAM
</SYSTEM_RAM_INFO>

<BLOCK_DEVICE_INFO>
/dev/sda6: TYPE="ext4"
/dev/sda7: TYPE="ext4"
/dev/sda8: TYPE="ext4"
</BLOCK_DEVICE_INFO>

<AVAILABLE_IRQ_INFO>
3, 4, 5, 6, 7, 10, 11, 13, 14, 15
</AVAILABLE_IRQ_INFO>

<TOTAL_MEM_INFO>
8032796 kB
</TOTAL_MEM_INFO>

<CPU_PROCESSOR_INFO>
0, 1, 2, 3
</CPU_PROCESSOR_INFO>

</acrn-config>

From: acrn-users@... <acrn-users@...> on behalf of Victor Sun <victor.sun@...>
Sent: Saturday, November 16, 2019 7:50 AM
To: acrn-users@... <acrn-users@...>
Subject: Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop
 

Hi Rajagopal,

Could you please share your board xml file?

If there is no UART in your laptop, ACRN should be OK to run if no configuration conflict but it is hard to debug when issue happens.
BR,
Victor

On 11/15/2019 11:33 PM, a.rajagopal via Lists.Projectacrn.Org wrote:
Hello Victor,

>>Make sure your code include below commit:

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c

With the above commit, I run into the below error ...


..../board_cfg_lib.py", line 339, in parser_vuart_console

 

    if ttys and 'BDF' in ttys[0] or '/dev' in ttys[0]:

TypeError: argument of type 'NoneType' is not iterable


My laptop doesn't have RS232/DB9 port, is it mandatory or how to skip ?

Thanks,
Rajagopal

Disclaimer: "This message is intended only for the designated recipient(s). It may contain confidential or proprietary information and may be subject to other confidentiality protections. If you are not a designated recipient, you may not review, copy or distribute this message. Please notify the sender by e-mail and delete this message. GlobalEdge does not accept any liability for virus infected mails."


Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Rajagopal Aravindan
 

Hello Victor,

>>Could you please share your board xml file?
PFB (my signature) the board xml.

Thanks,
Rajagopal

<acrn-config board="lenl450">
<BIOS_INFO>
BIOS Information
Vendor: LENOVO
Version: JDET55WW (1.17 )
Release Date: 11/20/2015
BIOS Revision: 1.17
</BIOS_INFO>

<BASE_BOARD_INFO>
Base Board Information
Manufacturer: LENOVO
Product Name: Intel powered classmate PC
Version: SDK0E50510 WIN
</BASE_BOARD_INFO>

<PCI_DEVICE>
00:00.0 Host bridge: Intel Corporation Broadwell-U Host Bridge -OPI (rev 09)
00:02.0 VGA compatible controller: Intel Corporation HD Graphics 5500 (rev 09)
Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at c0000000 (64-bit, prefetchable) [size=512M]
00:03.0 Audio device: Intel Corporation Broadwell-U Audio Controller (rev 09)
Region 0: Memory at e1230000 (64-bit, non-prefetchable) [size=16K]
00:14.0 USB controller: Intel Corporation Wildcat Point-LP USB xHCI Controller (rev 03)
Region 0: Memory at e1220000 (64-bit, non-prefetchable) [size=64K]
00:16.0 Communication controller: Intel Corporation Wildcat Point-LP MEI Controller #1 (rev 03)
Region 0: Memory at e1239000 (64-bit, non-prefetchable) [size=32]
00:19.0 Ethernet controller: Intel Corporation Ethernet Connection (3) I218-LM (rev 03)
Region 0: Memory at e1200000 (32-bit, non-prefetchable) [size=128K]
Region 1: Memory at e123e000 (32-bit, non-prefetchable) [size=4K]
00:1b.0 Audio device: Intel Corporation Wildcat Point-LP High Definition Audio Controller (rev 03)
Region 0: Memory at e1234000 (64-bit, non-prefetchable) [size=16K]
00:1c.0 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #1 (rev e3)
00:1c.2 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #3 (rev e3)
00:1c.5 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #6 (rev e3)
00:1d.0 USB controller: Intel Corporation Wildcat Point-LP USB EHCI Controller (rev 03)
Region 0: Memory at e123d000 (32-bit, non-prefetchable) [size=1K]
00:1f.0 ISA bridge: Intel Corporation Wildcat Point-LP LPC Controller (rev 03)
00:1f.2 SATA controller: Intel Corporation Wildcat Point-LP SATA Controller [AHCI Mode] (rev 03)
Region 5: Memory at e123c000 (32-bit, non-prefetchable) [size=2K]
00:1f.3 SMBus: Intel Corporation Wildcat Point-LP SMBus Controller (rev 03)
Region 0: Memory at e1238000 (64-bit, non-prefetchable) [size=256]
00:1f.6 Signal processing controller: Intel Corporation Wildcat Point-LP Thermal Management Controller (rev 03)
Region 0: Memory at e123b000 (64-bit, non-prefetchable) [size=4K]
04:00.0 Network controller: Intel Corporation Wireless 7265 (rev 61)
Region 0: Memory at e1100000 (64-bit, non-prefetchable) [size=8K]
05:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTS5227 PCI Express Card Reader (rev 01)
Region 0: Memory at e1000000 (32-bit, non-prefetchable) [size=4K]
</PCI_DEVICE>

<PCI_VID_PID>
00:00.0 0600: 8086:1604 (rev 09)
00:02.0 0300: 8086:1616 (rev 09)
00:03.0 0403: 8086:160c (rev 09)
00:14.0 0c03: 8086:9cb1 (rev 03)
00:16.0 0780: 8086:9cba (rev 03)
00:19.0 0200: 8086:15a2 (rev 03)
00:1b.0 0403: 8086:9ca0 (rev 03)
00:1c.0 0604: 8086:9c90 (rev e3)
00:1c.2 0604: 8086:9c94 (rev e3)
00:1c.5 0604: 8086:9c9a (rev e3)
00:1d.0 0c03: 8086:9ca6 (rev 03)
00:1f.0 0601: 8086:9cc3 (rev 03)
00:1f.2 0106: 8086:9c83 (rev 03)
00:1f.3 0c05: 8086:9ca2 (rev 03)
00:1f.6 1180: 8086:9ca4 (rev 03)
04:00.0 0280: 8086:095b (rev 61)
05:00.0 ff00: 10ec:5227 (rev 01)
</PCI_VID_PID>

<WAKE_VECTOR_INFO>
#define WAKE_VECTOR_32          0xACF6800CUL
#define WAKE_VECTOR_64          0xACF68018UL
</WAKE_VECTOR_INFO>

<RESET_REGISTER_INFO>
#define RESET_REGISTER_ADDRESS  0xCF9UL
#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
#define RESET_REGISTER_VALUE    0x6U
</RESET_REGISTER_INFO>

<PM_INFO>
#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1A_EVT_BIT_WIDTH      0x20U
#define PM1A_EVT_BIT_OFFSET     0x0U
#define PM1A_EVT_ADDRESS        0x1800UL
#define PM1A_EVT_ACCESS_SIZE    0x2U
#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1B_EVT_BIT_WIDTH      0x0U
#define PM1B_EVT_BIT_OFFSET     0x0U
#define PM1B_EVT_ADDRESS        0x0UL
#define PM1B_EVT_ACCESS_SIZE    0x2U
#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1A_CNT_BIT_WIDTH      0x10U
#define PM1A_CNT_BIT_OFFSET     0x0U
#define PM1A_CNT_ADDRESS        0x1804UL
#define PM1A_CNT_ACCESS_SIZE    0x2U
#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
#define PM1B_CNT_BIT_WIDTH      0x0U
#define PM1B_CNT_BIT_OFFSET     0x0U
#define PM1B_CNT_ADDRESS        0x0UL
#define PM1B_CNT_ACCESS_SIZE    0x2U
</PM_INFO>

<S3_INFO>
</S3_INFO>

<S5_INFO>
</S5_INFO>

<DRHD_INFO>
#define DRHD_COUNT              2U

#define DRHD0_DEV_CNT           0x1U
#define DRHD0_SEGMENT           0x0U
#define DRHD0_FLAGS             0x0U
#define DRHD0_REG_BASE          0xFED90000UL
#define DRHD0_IGNORE            true
#define DRHD0_DEVSCOPE0_TYPE    0x1U
#define DRHD0_DEVSCOPE0_ID      0x0U
#define DRHD0_DEVSCOPE0_BUS     0x0U
#define DRHD0_DEVSCOPE0_PATH    0x10U

#define DRHD1_DEV_CNT           0x2U
#define DRHD1_SEGMENT           0x0U
#define DRHD1_FLAGS             0x1U
#define DRHD1_REG_BASE          0xFED91000UL
#define DRHD1_IGNORE            false
#define DRHD1_DEVSCOPE0_TYPE    0x3U
#define DRHD1_DEVSCOPE0_ID      0x2U
#define DRHD1_DEVSCOPE0_BUS     0xf0U
#define DRHD1_DEVSCOPE0_PATH    0xf8U
#define DRHD1_DEVSCOPE1_TYPE    0x4U
#define DRHD1_DEVSCOPE1_ID      0x0U
#define DRHD1_DEVSCOPE1_BUS     0xf0U
#define DRHD1_DEVSCOPE1_PATH    0x78U

</DRHD_INFO>

<CPU_BRAND>
"Intel(R) Core(TM) i5-5300U CPU @ 2.30GHz"
</CPU_BRAND>

<CX_INFO>
/* Cx data is not available */
</CX_INFO>

<PX_INFO>
{0x8FDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001D00UL, 0x001D00UL}, /* P0 */
{0x8FCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL}, /* P1 */
{0x898UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001600UL, 0x001600UL}, /* P2 */
{0x7D0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001400UL, 0x001400UL}, /* P3 */
{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P4 */
{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P5 */
{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P6 */
{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P7 */
{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P8 */
{0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */
{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P10 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P11 */
{0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P12 */
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P13 */
{0x258UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000600UL, 0x000600UL}, /* P14 */
{0x1F4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000500UL, 0x000500UL}, /* P15 */
</PX_INFO>

<CLOS_INFO>
clos supported by cache:False
clos max:0
</CLOS_INFO>

<TTYS_INFO>
</TTYS_INFO>

<SYSTEM_RAM_INFO>
00001000-00057fff : System RAM
00059000-0008bfff : System RAM
00100000-a9efdfff : System RAM
acfff000-acffffff : System RAM
100000000-24dffffff : System RAM
</SYSTEM_RAM_INFO>

<BLOCK_DEVICE_INFO>
/dev/sda6: TYPE="ext4"
/dev/sda7: TYPE="ext4"
/dev/sda8: TYPE="ext4"
</BLOCK_DEVICE_INFO>

<AVAILABLE_IRQ_INFO>
3, 4, 5, 6, 7, 10, 11, 13, 14, 15
</AVAILABLE_IRQ_INFO>

<TOTAL_MEM_INFO>
8032796 kB
</TOTAL_MEM_INFO>

<CPU_PROCESSOR_INFO>
0, 1, 2, 3
</CPU_PROCESSOR_INFO>

</acrn-config>

From: acrn-users@... <acrn-users@...> on behalf of Victor Sun <victor.sun@...>
Sent: Saturday, November 16, 2019 7:50 AM
To: acrn-users@... <acrn-users@...>
Subject: Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop
 

Hi Rajagopal,

Could you please share your board xml file?

If there is no UART in your laptop, ACRN should be OK to run if no configuration conflict but it is hard to debug when issue happens.
BR,
Victor

On 11/15/2019 11:33 PM, a.rajagopal via Lists.Projectacrn.Org wrote:
Hello Victor,

>>Make sure your code include below commit:

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c

With the above commit, I run into the below error ...


..../board_cfg_lib.py", line 339, in parser_vuart_console

 

    if ttys and 'BDF' in ttys[0] or '/dev' in ttys[0]:

TypeError: argument of type 'NoneType' is not iterable


My laptop doesn't have RS232/DB9 port, is it mandatory or how to skip ?

Thanks,
Rajagopal

Disclaimer: "This message is intended only for the designated recipient(s). It may contain confidential or proprietary information and may be subject to other confidentiality protections. If you are not a designated recipient, you may not review, copy or distribute this message. Please notify the sender by e-mail and delete this message. GlobalEdge does not accept any liability for virus infected mails."


Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Victor Sun
 

Hi Rajagopal,

Could you please share your board xml file?

If there is no UART in your laptop, ACRN should be OK to run if no configuration conflict but it is hard to debug when issue happens.
BR,
Victor

On 11/15/2019 11:33 PM, a.rajagopal via Lists.Projectacrn.Org wrote:

Hello Victor,

>>Make sure your code include below commit:

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c

With the above commit, I run into the below error ...


..../board_cfg_lib.py", line 339, in parser_vuart_console

 

    if ttys and 'BDF' in ttys[0] or '/dev' in ttys[0]:

TypeError: argument of type 'NoneType' is not iterable


My laptop doesn't have RS232/DB9 port, is it mandatory or how to skip ?

Thanks,
Rajagopal


Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Rajagopal Aravindan
 

Hello Victor,

>>Make sure your code include below commit:

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c

With the above commit, I run into the below error ...


..../board_cfg_lib.py", line 339, in parser_vuart_console

 

    if ttys and 'BDF' in ttys[0] or '/dev' in ttys[0]:

TypeError: argument of type 'NoneType' is not iterable


My laptop doesn't have RS232/DB9 port, is it mandatory or how to skip ?

Thanks,
Rajagopal


Re: ACRN on NUC5CPYH

Victor Sun
 

hi Rajagopal,

Please try below:

disable vt-d in bios, do cold power boot, re-enable vt-d in bios, do cold power boot again.

If DMAR still can not present, you need to contact bios vendor.


Also, please check the result of "virt-host-validate" in native, if DMAR doesn't present, then you also have problem to run KVM/Xen...

BR,

Victor


On 11/15/2019 1:40 AM, Rajagopal Aravindan wrote:

Hello Victor,

>> Yes, DMAR table might not exist if vt-d is disabled in BIOS.
On our NUC, we have VT-d enabled in VisualBIOS but, there is NO option for IPU.
How do we get DMAR tables in this case ?

Thanks,
Rajagopal

On Fri, Nov 8, 2019 at 6:13 AM Victor Sun <victor.sun@...> wrote:

Yes, DMAR table might not exist if vt-d is disabled in BIOS.

BR,

Victor

On 11/8/2019 1:57 AM, Dubravko Moravski | Exor Embedded S.r.l. wrote:
Hello Rajagopal,

I'm not an expert but just a user of ACRN; we've had a similar issue on one of our boards. To enable DMAR table in ACPI, ensure in BIOS settings that IPU is disabled, and VT-d instructions are enabled. If you still have the same error, you'll have to ask your BIOS provider to add the DMAR table.

Regards,
Dubravko


From: acrn-users@... <acrn-users@...> on behalf of Rajagopal Aravindan via Lists.Projectacrn.Org <a.rajagopal.81=gmail.com@...>
Sent: Thursday, November 7, 2019 4:43 PM
To: victor.sun@... <victor.sun@...>
Cc: acrn-dev@... <acrn-dev@...>; acrn-users@... <acrn-users@...>
Subject: [acrn-users] ACRN on NUC5CPYH
 
Hello Victor,

We are also trying to run ACRN on NUC5CPYH.
PFA the following ...
  1. screenshot of the error while running board_parser.py
  2. o/p of cat /proc/cpuinfo
  3. screenshot of VisualBios details, currently configured to UEFI-only mode
Can you please help us get past this ?

Thanks,
Rajagopal

Dubravko Moravski
SW engineering
Exor Embedded S.r.l.
p: +38 512455659  m: +38 5915402413
a: Slavonska avenija, 50, Zagreb, Croatia, 10000
w: exorint.com 

 Prima di stampare pensa ai costi ambientali. Please consider the environment before printing this email.

Privacy


Re: ACRN on NUC5CPYH

Rajagopal Aravindan
 

Hello Victor,

>> Yes, DMAR table might not exist if vt-d is disabled in BIOS.
On our NUC, we have VT-d enabled in VisualBIOS but, there is NO option for IPU.
How do we get DMAR tables in this case ?

Thanks,
Rajagopal


On Fri, Nov 8, 2019 at 6:13 AM Victor Sun <victor.sun@...> wrote:

Yes, DMAR table might not exist if vt-d is disabled in BIOS.

BR,

Victor

On 11/8/2019 1:57 AM, Dubravko Moravski | Exor Embedded S.r.l. wrote:
Hello Rajagopal,

I'm not an expert but just a user of ACRN; we've had a similar issue on one of our boards. To enable DMAR table in ACPI, ensure in BIOS settings that IPU is disabled, and VT-d instructions are enabled. If you still have the same error, you'll have to ask your BIOS provider to add the DMAR table.

Regards,
Dubravko


From: acrn-users@... <acrn-users@...> on behalf of Rajagopal Aravindan via Lists.Projectacrn.Org <a.rajagopal.81=gmail.com@...>
Sent: Thursday, November 7, 2019 4:43 PM
To: victor.sun@... <victor.sun@...>
Cc: acrn-dev@... <acrn-dev@...>; acrn-users@... <acrn-users@...>
Subject: [acrn-users] ACRN on NUC5CPYH
 
Hello Victor,

We are also trying to run ACRN on NUC5CPYH.
PFA the following ...
  1. screenshot of the error while running board_parser.py
  2. o/p of cat /proc/cpuinfo
  3. screenshot of VisualBios details, currently configured to UEFI-only mode
Can you please help us get past this ?

Thanks,
Rajagopal

Dubravko Moravski
SW engineering
Exor Embedded S.r.l.
p: +38 512455659  m: +38 5915402413
a: Slavonska avenija, 50, Zagreb, Croatia, 10000
w: exorint.com 

 Prima di stampare pensa ai costi ambientali. Please consider the environment before printing this email.

Privacy


Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Victor Sun
 

Hi Rajagopal,

Please refer : https://github.com/projectacrn/acrn-hypervisor/commit/cdd086a81d5997d52ace5a541c9b1e99ce35c24c

Please rebase to the lastest, this commit is merged yesterday.
BR,
Victor

On 11/14/2019 12:32 PM, Rajagopal Aravindan wrote:

Hello Victor

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c
I don't see this commit id in the master here : https://github.com/projectacrn/acrn-hypervisor/tree/master
Has it been upstreamed or should I look it up from elsewhere  ?

Please do clarify.

Thanks,
Rajagopal

On Wed, Nov 13, 2019 at 7:34 AM Victor Sun <victor.sun@...> wrote:

Make sure your code include below commit:

commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c
Author: Wei Liu <weix.w.liu@...>
Date:   Tue Nov 12 09:18:20 2019 +0800

    acrn-config: by-pass acpi_idle/acpi_cpufreq for parsing target board
   
    Current board parse logic would be broken if acpi_idle/acpi-cpufreq
    driver is not loaded by native kernel.
    This patch would just leave a warning to user and continue to parse
    other information in this case.
   
    Tracked-On: #4082
    Signed-off-by: Wei Liu <weix.w.liu@...>
    Acked-by: Victor Sun <victor.sun@...>

BR,

Victor

On 11/12/2019 10:19 PM, Victor Sun wrote:

Hi Rajagopal,

Please try the latest code, the acpi_idle driver check will be ignored if ACPI Cstate is not enabled in BIOS.

But you need to be aware that Cstate will not be supported in ACRN in this case.

BR,

Victor

On 11/12/2019 9:07 AM, Victor Sun wrote:

Hi Rajagopal,

This most likely you didn't enable ACPI Cstate in BIOS. Please double check.

We are working on a patch that bypass acpi_idle/acpi_cpufreq driver checking soon, will keep you posted when it is ready.

BR,

Victor

On 11/11/2019 10:46 PM, Rajagopal Aravindan wrote:
Hello Victor,

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.
PFA the relevant files.

Can you please help on what we are doing wrong here ?

Thanks,
Rajagopal



Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Rajagopal Aravindan
 

Hello Victor

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c
I don't see this commit id in the master here : https://github.com/projectacrn/acrn-hypervisor/tree/master
Has it been upstreamed or should I look it up from elsewhere  ?

Please do clarify.

Thanks,
Rajagopal

On Wed, Nov 13, 2019 at 7:34 AM Victor Sun <victor.sun@...> wrote:

Make sure your code include below commit:

commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c
Author: Wei Liu <weix.w.liu@...>
Date:   Tue Nov 12 09:18:20 2019 +0800

    acrn-config: by-pass acpi_idle/acpi_cpufreq for parsing target board
   
    Current board parse logic would be broken if acpi_idle/acpi-cpufreq
    driver is not loaded by native kernel.
    This patch would just leave a warning to user and continue to parse
    other information in this case.
   
    Tracked-On: #4082
    Signed-off-by: Wei Liu <weix.w.liu@...>
    Acked-by: Victor Sun <victor.sun@...>

BR,

Victor

On 11/12/2019 10:19 PM, Victor Sun wrote:

Hi Rajagopal,

Please try the latest code, the acpi_idle driver check will be ignored if ACPI Cstate is not enabled in BIOS.

But you need to be aware that Cstate will not be supported in ACRN in this case.

BR,

Victor

On 11/12/2019 9:07 AM, Victor Sun wrote:

Hi Rajagopal,

This most likely you didn't enable ACPI Cstate in BIOS. Please double check.

We are working on a patch that bypass acpi_idle/acpi_cpufreq driver checking soon, will keep you posted when it is ready.

BR,

Victor

On 11/11/2019 10:46 PM, Rajagopal Aravindan wrote:
Hello Victor,

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.
PFA the relevant files.

Can you please help on what we are doing wrong here ?

Thanks,
Rajagopal



ACRN Project Technical Community Meeting Minutes - 11/13/2019

Wang, Hongbo
 

 
ACRN Project TCM - 13th Nov 2019
Location
Agenda
  1. ACRN project update 
  • ACRN v1.4 will release within this week.
 
  1. “ACRN Schedule Framework Introduction” by LIU, Shuo
Download foil from ACRN Presentation->ACRN_TCM->WW46’19
Short description: ACRN has a simple scheduling system and has no scheduler concept before, because early usage of ACRN is core logical partition mode which doesn’t need vCPUs sharing. Today, we reshuffle the scheduler framework and make it easier to expand with different schedule policy. We abstract scheduler which isolates from scheduling framework. ACRN can pick one scheduler at boot time and run its schedule policy.
 
  1. All: Community open discussion.
 
  1. Next meeting agenda proposal:
 
WW Topic Presenter Status
WW02 TPM2.0 virtualization in ACRN DENG, Wei 1/9
WW03 Polling mode Virtio and its advantage for RT VM DENG, Jie 1/16
WW04 Buffer sharing from UOS to SOS, HyperDMA usage LIU, Xinyun 1/23
WW05 USB HUB Virtualization WU, Xiaoguang 1/30
WW07 ACRN Device Model QoS Design LIU, Long 2/13
WW08 ACRN Debug Tips CHEN, Jason 2/20
WW09 GVT-g debug trace tool GONG, Zhipeng 2/27
WW10 Kata Container Architecture: First Steps with ACRN Dhanraj, Vijay  3/6
WW11 One ACRN hypervisor to support multi-platform WU, Xiangyang 3/13
WW12 Power button key mediator design in ACRN LIU, Yuan 3/20
WW13 Local APIC Virtualization Enhancement for Intel KBL platform LI, Fei 3/27
WW14 Safety VM Support YIN, FengWei 4/3
WW15 How to customize GPIO in ACRN LIU, Yuan 4/10
WW16 ACRN Cache QoS support based on CAT TAO, Yuhong 4/17
WW17 ACRN Real-Time measurement Methodology LI, Wilson 4/24
WW19 I2C Virtualization CHEN, Conghui 5/8
WW20 SGX Virtualization in ACRN WU, Binbin 5/15
WW21 Logger Improvement on acrn-dm CAO, Minggui 5/22
WW22 AcrnGT Virtual Display Deep Dive HE, Min 5/29
WW23 Local APIC Emulation and Pass-through Grandhi, Sainath 6/5
WW25
 
ACRN Functional Safety: Understanding and Mitigating Inter-VM Interference MAO, Junjie 6/19
WW26 Enable VwWorks as RTVM on ACRN FU, Kaige 6/26
WW27 ACRN 2.0 New Architecture Sharing - 1/2 REN, Jack 7/3
WW28 ACRN 2.0 New Architecture Sharing- 2/2 REN, Jack 7/10
WW29 How to enable open vSwitch on ACRN LIU, Yuan 7/17
WW30 ACRN Configuration Design Tool SUN, Victor 7/24
WW31 Design of GOP Driver for GVT-g HE, Min 7/31
WW32 Restricting Dynamic Resources from functional safety perspective MAO, Junjie 8/7
WW33 Android Virtual Secure Boot and key enrollment QI, Yadong/Zhao Shirley 8/14
WW34 Split ACRN’s Device Model CHEN, Jason CJ 8/21
WW35 ACRN Continuous Integration System Introduction ZHANG, Wenling 8/28
WW36 BKC for ACRN RT and vmexit analysis YAN, Like 9/4
WW37 ACRN Windows As A Guest (WaaG) Overview WANG, Yu1 9/11
WW38 ACRN Fuzzing Test HUANG, Yonghua 9/18
WW39 Implementation of GOP driver with AcrnGT LIU, Xinyun 9/25
WW41 Banish the Dead: Identifying and Removing Dead Code for Functional Safety MAO, Junjie 10/9
WW42 ACRN Memory Bandwidth Allocation (MBA) Dhanraj, Vijay 10/16
WW43 Enable OVMF for Service VM Wang, Qian 10/23
WW44 Windows As A Guest and HLK Introduction SHEN, Fangfang 10/29
WW45 Performance Monitoring Unit Introduction WU, Binbin 11/6
 
Marketing/Events
  1.  
Resources
  1. Project URL: 
  1. Portal: https://projectacrn.org   
  2. Source code: https://github.com/projectacrn   
  3. email: info@... 
  4. Technical Mailing list: acrn-dev@... 
  1. Recommended Hardware platform (reference):
  1. Apollo Lake (SoC) UP2 (with serial port): AAEON UPS-APLC2-A10-0232 
  2. Apollo Lake (SoC) NUC (without serial port): NUC6CAYHL (at least 8G memory)
  3. Kabylake (Core) NUC (with serial port): NUC7i5DNHE
 
=======================
 
 
 
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
 
 


Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Victor Sun
 

Make sure your code include below commit:

commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c
Author: Wei Liu <weix.w.liu@...>
Date:   Tue Nov 12 09:18:20 2019 +0800

    acrn-config: by-pass acpi_idle/acpi_cpufreq for parsing target board
   
    Current board parse logic would be broken if acpi_idle/acpi-cpufreq
    driver is not loaded by native kernel.
    This patch would just leave a warning to user and continue to parse
    other information in this case.
   
    Tracked-On: #4082
    Signed-off-by: Wei Liu <weix.w.liu@...>
    Acked-by: Victor Sun <victor.sun@...>

BR,

Victor

On 11/12/2019 10:19 PM, Victor Sun wrote:

Hi Rajagopal,

Please try the latest code, the acpi_idle driver check will be ignored if ACPI Cstate is not enabled in BIOS.

But you need to be aware that Cstate will not be supported in ACRN in this case.

BR,

Victor

On 11/12/2019 9:07 AM, Victor Sun wrote:

Hi Rajagopal,

This most likely you didn't enable ACPI Cstate in BIOS. Please double check.

We are working on a patch that bypass acpi_idle/acpi_cpufreq driver checking soon, will keep you posted when it is ready.

BR,

Victor

On 11/11/2019 10:46 PM, Rajagopal Aravindan wrote:
Hello Victor,

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.
PFA the relevant files.

Can you please help on what we are doing wrong here ?

Thanks,
Rajagopal



Recall: [acrn-users] ACRN on ThinkPad-L450 laptop

Yao, Michael
 

Yao, Michael would like to recall the message, "[acrn-users] ACRN on ThinkPad-L450 laptop".


Re: ACRN on ThinkPad-L450 laptop

Yao, Michael
 

Avoid “latest”… use a specific commit id or tag.

 

From: acrn-users@... <acrn-users@...> On Behalf Of Victor Sun
Sent: Tuesday, November 12, 2019 10:19 PM
To: Rajagopal Aravindan <a.rajagopal.81@...>
Cc: acrn-dev@...; acrn-users@...
Subject: Re: [acrn-users] ACRN on ThinkPad-L450 laptop

 

Hi Rajagopal,

Please try the latest code, the acpi_idle driver check will be ignored if ACPI Cstate is not enabled in BIOS.

But you need to be aware that Cstate will not be supported in ACRN in this case.

BR,

Victor

On 11/12/2019 9:07 AM, Victor Sun wrote:

Hi Rajagopal,

This most likely you didn't enable ACPI Cstate in BIOS. Please double check.

We are working on a patch that bypass acpi_idle/acpi_cpufreq driver checking soon, will keep you posted when it is ready.

BR,

Victor

On 11/11/2019 10:46 PM, Rajagopal Aravindan wrote:

Hello Victor,

 

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.

PFA the relevant files.

 

Can you please help on what we are doing wrong here ?

 

Thanks,

Rajagopal

 

 


Re: ACRN on ThinkPad-L450 laptop

Victor Sun
 

Hi Rajagopal,

Please try the latest code, the acpi_idle driver check will be ignored if ACPI Cstate is not enabled in BIOS.

But you need to be aware that Cstate will not be supported in ACRN in this case.

BR,

Victor

On 11/12/2019 9:07 AM, Victor Sun wrote:

Hi Rajagopal,

This most likely you didn't enable ACPI Cstate in BIOS. Please double check.

We are working on a patch that bypass acpi_idle/acpi_cpufreq driver checking soon, will keep you posted when it is ready.

BR,

Victor

On 11/11/2019 10:46 PM, Rajagopal Aravindan wrote:
Hello Victor,

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.
PFA the relevant files.

Can you please help on what we are doing wrong here ?

Thanks,
Rajagopal



ACRN Project Technical Community Meeting (2019/7~2019/12): @ Weekly Wednesday 11AM (China-Shanghai), Tuesday 7PM (US-West Coast), Wednesday 3AM (Europe-London)

Wang, Hongbo
 

Notice: Join ACRN’s TCM meeting with WebEx till Nov. 2019
Due to Zoom’s connection issue in PRC mainland recently, we have to use WebEx to replace Zoom for ACRN TCM meeting temporarily. We’ll monitor Zoom’s availability closely and switch back to Zoom as it comes back to normal. Sorry for the inconvenience!
Cisco WebEx: https://intel.webex.com/intel/j.php?MTID=md8485ef1ef04eeee01805a7cb323801b  (More details is at the bottom of the meeting request)
 
 
Date: 11/13
Topic:  ACRN Schedule Framework Introduction
Description: ACRN has a simple scheduling system and has no scheduler concept before, because early usage of ACRN is core logical partition mode which doesn’t need vCPUs sharing. Today, we reshuffle the scheduler framework and make it easier to expand with different schedule policy. We abstract scheduler which isolates from scheduling framework. ACRN can pick one scheduler at boot time and run its schedule policy.
 
WW Topic Presenter Status
WW02 TPM2.0 virtualization in ACRN DENG, Wei 1/9
WW03 Polling mode Virtio and its advantage for RT VM DENG, Jie 1/16
WW04 Buffer sharing from UOS to SOS, HyperDMA usage LIU, Xinyun 1/23
WW05 USB HUB Virtualization WU, Xiaoguang 1/30
WW07 ACRN Device Model QoS Design LIU, Long 2/13
WW08 ACRN Debug Tips CHEN, Jason 2/20
WW09 GVT-g debug trace tool GONG, Zhipeng 2/27
WW10 Kata Container Architecture: First Steps with ACRN Dhanraj, Vijay  3/6
WW11 One ACRN hypervisor to support multi-platform WU, Xiangyang 3/13
WW12 Power button key mediator design in ACRN LIU, Yuan 3/20
WW13 Local APIC Virtualization Enhancement for Intel KBL platform LI, Fei 3/27
WW14 Safety VM Support YIN, FengWei 4/3
WW15 How to customize GPIO in ACRN LIU, Yuan 4/10
WW16 ACRN Cache QoS support based on CAT TAO, Yuhong 4/17
WW17 ACRN Real-Time measurement Methodology LI, Wilson 4/24
WW19 I2C Virtualization CHEN, Conghui 5/8
WW20 SGX Virtualization in ACRN WU, Binbin 5/15
WW21 Logger Improvement on acrn-dm CAO, Minggui 5/22
WW22 AcrnGT Virtual Display Deep Dive HE, Min 5/29
WW23 Local APIC Emulation and Pass-through Grandhi, Sainath 6/5
WW25
 
ACRN Functional Safety: Understanding and Mitigating Inter-VM Interference MAO, Junjie 6/19
WW26 Enable VwWorks as RTVM on ACRN FU, Kaige 6/26
WW27 ACRN 2.0 New Architecture Sharing - 1/2 REN, Jack 7/3
WW28 ACRN 2.0 New Architecture Sharing- 2/2 REN, Jack 7/10
WW29 How to enable open vSwitch on ACRN LIU, Yuan 7/17
WW30 ACRN Configuration Design Tool SUN, Victor 7/24
WW31 Design of GOP Driver for GVT-g HE, Min 7/31
WW32 On Dynamic Resource Allocation Mao, Junjie 8/7
WW33 ACRN virtual secure boot and key enrollment Wang, Kai 8/14
WW34 Split ACRN’s Device Model CHEN, Jason CJ 8/21
WW35 ACRN Continuous Integration System Introduction ZHANG, Wenling 8/28
WW36 BKC for ACRN RT and vmexit analysis YAN, Like 9/4
WW37 ACRN Windows As A Guest (WaaG) Overview CHEN, Jianjun 9/11
WW38 ACRN Fuzzing Test HUANG, Yonghua 9/18
WW39 Implementation of GOP driver with AcrnGT LIU, Xinyun 9/25
WW41 Banish the Dead: Identifying and Removing Dead Code for Functional Safety MAO, Junjie 10/9
WW42 ACRN Memory Bandwidth Allocation (MBA) Vijay Dhanraj 10/16
WW43 Enable OVMF for Service VM WANG, Qian 10/23
WW44 WaaG and Its HLK SHEN, Fangfang 10/30
WW45 Performance Monitoring Unit Introduction WU, Binbin 11/6
WW46 ACRN Schedule Framework Introduction LIU, Shuo 11/13
 
 
 
Project ACRN: A flexible, light-weight, open source reference hypervisor for IoT devices
 
We're still in the early stages of forming this TSC, so instead we invite you to attend a weekly "Technical Community" meeting where we'll meet community members and talk about the ACRN project and plans. As we explore community interest and involvement opportunities, we'll (re)schedule these meetings at a time convenient to most attendees:
  • -- Do not delete or change any of the following text. --  
  • When it's time, join your Webex meeting here.
 
 
Meeting number (access code): 590 576 334
Meeting password: ShFp3MC@ 
 
 
Join
 
 
 
 
Join by phone 
Tap to call in from a mobile device (attendees only) 
+1-210-795-1110 US Toll 
+1-866-662-9987 US Toll Free 
Global call-in numbers  |  Toll-free calling restrictions  
 
Join from a video system or application
Dial 590576334@... 
You can also dial 173.243.2.68 and enter your meeting number.  
 
 
 
 
  • Meeting Notes:
 
 
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
 
 
 
 
 
 
 
 
 


Re: ACRN on ThinkPad-L450 laptop

Victor Sun
 

Hi Rajagopal,

This most likely you didn't enable ACPI Cstate in BIOS. Please double check.

We are working on a patch that bypass acpi_idle/acpi_cpufreq driver checking soon, will keep you posted when it is ready.

BR,

Victor

On 11/11/2019 10:46 PM, Rajagopal Aravindan wrote:

Hello Victor,

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.
PFA the relevant files.

Can you please help on what we are doing wrong here ?

Thanks,
Rajagopal



ACRN on ThinkPad-L450 laptop

Rajagopal Aravindan
 

Hello Victor,

W.r.t the subject, we are getting the error "Error:acpi_idle driver is not found." when running board_parser.py.
PFA the relevant files.

Can you please help on what we are doing wrong here ?

Thanks,
Rajagopal


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