Date   

Re: Support for NVMe drives in ACRN

Geoffroy Van Cutsem
 

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Chaohong guo
Sent: Wednesday, September 26, 2018 5:49 AM
To: acrn-users@...
Subject: Re: [acrn-users] Support for NVMe drives in ACRN


Do u check the boot order in UEFI BIOS ? Generally, the boot order is under
the control of BIOS. UEFI bios should have a watchdog timer, if the first
boot item didn't call exit-boot-service, BIOS will try to boot the next item in
boot order list.
The boot order in the Bios is correct, i.e. it loads acrn.efi first, but then nothing happens. I do not see the Clear Linux bootloader menu (from systemd-boot). As soon as I physically remove the NVMe drive, it loads acrn.efi and shows the Clear Linux bootloader. I'm able to bring the Service OS up after that.

I have tried on a different machine (same family, NUC7i7BNKQ), with Ubuntu 16.04 installed on the NVMe device (so different than the first system I was testing with) and I see the same problem.

I have upgraded both machines to the latest Bios (version 0069) but I still see the problem.

Note that the watchdog timer does not seem to work here, and even if it did, it wouldn't help me too much as my objective is to actually boot ACRN (so moving on to a next boot entry that wouldn't load ACRN does not help me).

Thanks,
Geoffroy



-Chaohong


-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Wang, Hongbo
Sent: Wednesday, September 26, 2018 9:45 AM
To: acrn-users@...
Subject: Re: [acrn-users] Support for NVMe drives in ACRN

We haven't tried such combination before, will have a try and reply later.


Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
Mail: hongbo.wang@...

-----Original Message-----
From: acrn-users@...
[mailto:acrn-users@...] On Behalf Of Geoffroy Van
Cutsem
Sent: Tuesday, September 25, 2018 11:42 PM
To: acrn-users@...
Subject: [acrn-users] Support for NVMe drives in ACRN

Hi folks,

I have a NUC7i7BNH [1] that is equipped with both a NVMe and SATA
SSD drive. I have Clear Linux 25130 installed on the SSD (SATA).
There are a number of partitions on the NVMe drive but I'm not using
any of those at the moment. I have observed that the ACRN hypervisor
does not start correctly when the NVMe drive is installed. I don't
know exactly what is happening since I don't have a serial cable
hooked up to it but I never see the Clear Linux bootloader coming
up. As soon as I physically remove the NVMe drive, I can see that
bootloader (the Service OS is not coming up but I am treating this as a
different problem).

Is this a known issue?

Geoffroy

[1]
https://www.intel.com/content/www/us/en/products/boards-
kits/nuc/kits/
nuc7i7bnh.html





Re: Support for NVMe drives in ACRN

Chaohong guo <chaohong.guo@...>
 

Do u check the boot order in UEFI BIOS ? Generally, the boot order is under the control of BIOS. UEFI bios should have a watchdog timer, if the first boot item didn't call exit-boot-service, BIOS will try to boot the next item in boot order list.


-Chaohong

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Wang, Hongbo
Sent: Wednesday, September 26, 2018 9:45 AM
To: acrn-users@...
Subject: Re: [acrn-users] Support for NVMe drives in ACRN

We haven't tried such combination before, will have a try and reply later.


Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
Mail: hongbo.wang@...

-----Original Message-----
From: acrn-users@...
[mailto:acrn-users@...] On Behalf Of Geoffroy Van
Cutsem
Sent: Tuesday, September 25, 2018 11:42 PM
To: acrn-users@...
Subject: [acrn-users] Support for NVMe drives in ACRN

Hi folks,

I have a NUC7i7BNH [1] that is equipped with both a NVMe and SATA SSD
drive. I have Clear Linux 25130 installed on the SSD (SATA). There are
a number of partitions on the NVMe drive but I'm not using any of
those at the moment. I have observed that the ACRN hypervisor does not
start correctly when the NVMe drive is installed. I don't know exactly
what is happening since I don't have a serial cable hooked up to it
but I never see the Clear Linux bootloader coming up. As soon as I
physically remove the NVMe drive, I can see that bootloader (the
Service OS is not coming up but I am treating this as a different problem).

Is this a known issue?

Geoffroy

[1]
https://www.intel.com/content/www/us/en/products/boards-
kits/nuc/kits/
nuc7i7bnh.html




Re: Support for NVMe drives in ACRN

Wang, Hongbo
 

We haven't tried such combination before, will have a try and reply later.


Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
Mail: hongbo.wang@...

-----Original Message-----
From: acrn-users@...
[mailto:acrn-users@...] On Behalf Of Geoffroy Van Cutsem
Sent: Tuesday, September 25, 2018 11:42 PM
To: acrn-users@...
Subject: [acrn-users] Support for NVMe drives in ACRN

Hi folks,

I have a NUC7i7BNH [1] that is equipped with both a NVMe and SATA SSD
drive. I have Clear Linux 25130 installed on the SSD (SATA). There are a
number of partitions on the NVMe drive but I'm not using any of those at the
moment. I have observed that the ACRN hypervisor does not start correctly
when the NVMe drive is installed. I don't know exactly what is happening
since I don't have a serial cable hooked up to it but I never see the Clear
Linux bootloader coming up. As soon as I physically remove the NVMe drive,
I can see that bootloader (the Service OS is not coming up but I am treating
this as a different problem).

Is this a known issue?

Geoffroy

[1]
https://www.intel.com/content/www/us/en/products/boards-kits/nuc/kits/
nuc7i7bnh.html



Support for NVMe drives in ACRN

Geoffroy Van Cutsem
 

Hi folks,

I have a NUC7i7BNH [1] that is equipped with both a NVMe and SATA SSD drive. I have Clear Linux 25130 installed on the SSD (SATA). There are a number of partitions on the NVMe drive but I'm not using any of those at the moment. I have observed that the ACRN hypervisor does not start correctly when the NVMe drive is installed. I don't know exactly what is happening since I don't have a serial cable hooked up to it but I never see the Clear Linux bootloader coming up. As soon as I physically remove the NVMe drive, I can see that bootloader (the Service OS is not coming up but I am treating this as a different problem).

Is this a known issue?

Geoffroy

[1] https://www.intel.com/content/www/us/en/products/boards-kits/nuc/kits/nuc7i7bnh.html


[Announce] ACRN ver0.2 Release Notes

Wang, Hongbo
 

Hi all,

 

We are pleased to announce version 0.2 release of ACRN. You can see the Release Notes in the website https://projectacrn.github.io/latest/release_notes.html.

 

To learn more about ACRN: ACRN is a flexible, lightweight reference hypervisor, built with real-time and safety-criticality in mind, optimized to streamline embedded development through an open source platform. Check out the ACRN project portal (https://projectacrn.org/) for more information.

 

 

 

 

Best regards.

Hongbo

Tel: +86-21-6116 7445

MP: +86-1364 1793 689

Mail: hongbo.wang@...

 


ACRN Project Technical Community Meeting: @ Weekly 9PM-10PM (China-Shanghai), 6AM-7AM (US-West Coast), 3PM-4PM (Europe-London)

Wang, Hongbo
 

Agenda of 9/26: USB Virtualization in ACRN
Description: Not like server virtualization, devices virtualization is one of features for ACRN’s sharing mode usage. In this talk, presenter will introduce how to emulate USB xHCI (Host Controller) and USB xDCI (Device Controller) on Apollo Lake platform.
Your input and feedback are highly welcome!
 
WW Topic Presenter Status
WW21 ACRN roadmap introduction Ren, Jack Done
WW22 Patch submission process
ACRN feature list introduction
Wang, Hongbo
Ren, jack
Done
WW23 Memory Management Chen, Jascon Done
WW24 Boot flow and fast boot Wu, Binbin Done
WW25 Memory Management Chen, Jason C Done
WW26 Audio virtualization Li, Jocelyn Done
WW27 Trusty Security on ACRN Zhu, Bing’s team Done
WW28 Clear Linux and use on ACRN Du, Alek Done
WW29 GVT-g for ACRN (a.k.a AcrnGT) Gong, Zhipeng Done
WW30 Device pass-through Zhai, Edwin Done
WW31 ACRN logical partition Ren, Jack/Xu, Anthony Done
WW32 ACRN interrupt management Chen, Jason Done
WW33 ACRN ACPI virtualization Edwin Zhai Done
WW34 ACRN S3/S5 management Fengwei Yin Done
WW35 ACRN P-state/C-state management Victor Sun Done
WW36 CPU Virtualization Jason Chen Done
WW37 Design Review: ACRN Configuration Options Fengwei Yin Done
WW38 Remove Dynamic Memory Allocation Code in ACRN Li, Fei Done
WW39 USB virtualization Yu Wang 9/26
WW40 IPU Sharing Bandi, Kushal Plan
WW41 ACRN VT-d Binbin Wu Plan
WW42 ACRN GPIO virtualization Yu Wang Plan
 
 
Project ACRN: A flexible, light-weight, open source reference hypervisor for IoT devices
 
We're still in the early stages of forming this TSC, so instead we invite you to attend a weekly "Technical Community" meeting where we'll meet community members and talk about the ACRN project and plans. As we explore community interest and involvement opportunities, we'll (re)schedule these meetings at a time convenient to most attendees:
  • Meets every Wednesday, Starting May 30, 2018: 9PM-10PM (China-Shanghai), 6AM-7AM (US-West Coast)
  • Chairperson: Hongbo Wang, hongbo.wang@... (Intel)
  • Online conference link: https://zoom.us/j/880368975
  • Zoom Meeting ID: 880-368-975
  • Online conference phone:
  • US: +1 669 900 6833  or +1 646 558 8656   or +1 877 369 0926 (Toll Free) or +1 855 880 1246 (Toll Free)
  • China: +86 010 87833177  or 400 669 9381 (Toll Free)
  • Germany: +49 (0) 30 3080 6188  or +49 800 724 3138 (Toll Free)
  • Additional international phone numbers
  • Meeting Notes:
 
 
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
 
 
 
 


Re: ACRN support on UP2

Marathe, Yogesh
 

Hi,

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Geoffroy Van Cutsem
Sent: Monday, September 24, 2018 9:50 PM
To: acrn-users@...

On 09/21/2018 08:45 AM, Marathe, Yogesh wrote:
Hello,

I see there are 3 variants of SOC in UP2 datasheet
<https://up-board.org/wp-content/uploads/2016/05/UP-Square-
Datasheet
V0 .4.pdf> (Celeron, Pentium and Atom). Does ACRN support Atom
version?
If no, is there any plan to support Atom?
It should, because that is what it is being tested on - APL NUCs

On ACRN website
<https://projectacrn.github.io/latest/hardware.html#up-squared-boa
rd
, it mentions processor J3455 but there is no such part in UP2
data
sheet for SOC. If its Celeron, I believe it should be N3350 if
it’s a dual core part, right?
I'm a little confused by your statement above, that page mentions: "The UP2
features Intel Celeron N3550 and Intel Pentium N4200 SoCs. Both have been
confirmed to work with ACRN."

What am I missing?
Oh, I'm not sure if this updated recently but I could never find N3350 on ACRN page.
Thanks for pointing out, looks good now.

Thanks,
Geoffroy



https://ark.intel.com/products/95594/Intel-Celeron-Processor-J3455-2
M-
Cache-up-to-2_3-GHz

4 cores, no HT support.
UP2 doesn’t have J3455 version in the spec.

Auke





Re: ACRN support on UP2

Geoffroy Van Cutsem
 

Hi Yogesh,

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Marathe, Yogesh
Sent: Monday, September 24, 2018 4:20 PM
To: acrn-users@...
Subject: Re: [acrn-users] ACRN support on UP2

Hi Auke,

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Auke Kok
Sent: Monday, September 24, 2018 12:56 AM
To: acrn-users@...
Subject: Re: [acrn-users] ACRN support on UP2

On 09/21/2018 08:45 AM, Marathe, Yogesh wrote:
Hello,

I see there are 3 variants of SOC in UP2 datasheet
<https://up-board.org/wp-content/uploads/2016/05/UP-Square-
Datasheet
V0 .4.pdf> (Celeron, Pentium and Atom). Does ACRN support Atom
version?
If no, is there any plan to support Atom?
It should, because that is what it is being tested on - APL NUCs

On ACRN website
<https://projectacrn.github.io/latest/hardware.html#up-squared-board
, it mentions processor J3455 but there is no such part in UP2 data
sheet for SOC. If its Celeron, I believe it should be N3350 if it’s
a dual core part, right?
I'm a little confused by your statement above, that page mentions: "The UP2 features Intel Celeron N3550 and Intel Pentium N4200 SoCs. Both have been confirmed to work with ACRN."

What am I missing?

Thanks,
Geoffroy



https://ark.intel.com/products/95594/Intel-Celeron-Processor-J3455-2M-
Cache-up-to-2_3-GHz

4 cores, no HT support.
UP2 doesn’t have J3455 version in the spec.

Auke




Re: ACRN support on UP2

Marathe, Yogesh
 

Hi Auke,

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Auke Kok
Sent: Monday, September 24, 2018 12:56 AM
To: acrn-users@...
Subject: Re: [acrn-users] ACRN support on UP2

On 09/21/2018 08:45 AM, Marathe, Yogesh wrote:
Hello,

I see there are 3 variants of SOC in UP2 datasheet
<https://up-board.org/wp-content/uploads/2016/05/UP-Square-DatasheetV0
.4.pdf> (Celeron, Pentium and Atom). Does ACRN support Atom version?
If no, is there any plan to support Atom?
It should, because that is what it is being tested on - APL NUCs

On ACRN website
<https://projectacrn.github.io/latest/hardware.html#up-squared-board>,
it mentions processor J3455 but there is no such part in UP2 data
sheet for SOC. If its Celeron, I believe it should be N3350 if it’s a
dual core part, right?
https://ark.intel.com/products/95594/Intel-Celeron-Processor-J3455-2M-
Cache-up-to-2_3-GHz

4 cores, no HT support.
UP2 doesn’t have J3455 version in the spec.

Auke



Re: ACRN support on UP2

auke-jan.h.kok@...
 

On 09/21/2018 08:45 AM, Marathe, Yogesh wrote:
Hello,

I see there are 3 variants of SOC in UP2 datasheet
<https://up-board.org/wp-content/uploads/2016/05/UP-Square-DatasheetV0.4.pdf>
(Celeron, Pentium and Atom). Does ACRN support Atom version? If no, is
there any plan to support Atom?
It should, because that is what it is being tested on - APL NUCs

On ACRN website
<https://projectacrn.github.io/latest/hardware.html#up-squared-board>,
it mentions processor J3455 but there is no such part in UP2 data sheet
for SOC. If its Celeron, I believe it should be N3350 if it’s a dual
core part, right?
https://ark.intel.com/products/95594/Intel-Celeron-Processor-J3455-2M-Cache-up-to-2_3-GHz

4 cores, no HT support.

Auke


ACRN support on UP2

Marathe, Yogesh
 

Hello,

 

I see there are 3 variants of SOC in UP2 datasheet (Celeron, Pentium and Atom). Does ACRN support Atom version? If no, is there any plan to support Atom?

 

On ACRN website, it mentions processor J3455 but there is no such part in UP2 data sheet for SOC. If its Celeron, I believe it should be N3350 if it’s a dual core part, right?

 

Regards,

Yogesh.

 

P.S. mail to 'main@...' bounces, that’s where a new user would land up after following instructions on main website, an instruction to go to sub-groups (after registration) to find ‘acrn-users’ and ‘acrn-dev’ mailing lists will be really helpful for new users.

 


ACRN Project Technical Community Meeting Miutes - 9/19/2018

Wang, Hongbo
 

ACRN Project TCM - 19th September 2018
Location
Agenda
 
  1. ACRN project update
1.1 ACRN community survey: need to provide more technical docs, user case, invite joint design.
1.2 Open Source version Android (a.k.a “Celadon”) open sourced.
1.3 Slimboot Loader project open sourced. https://github.com/slimbootloader
 
  1. Li, Fei:  Try to remove dynamic memory allocation from ACRN memory management
Download foil from ACRN Presentation->ACRN_TCM->WW38’18.
  1. All: Community open discussion.
Q: MISRA C will apply to ACRN, SOS, DM? A: As first step, only ACRN hypervisor itself will  go through MISRA C compliance. It does not include the SOS yet. We may switch to VxWorks which is safety. In that case, we don’t to apply MISRA C to it. Otherwise, it requires more efforts. Then we can move to next level, like DM if it required.
Q: What is the safety integrity level ACRN targets at? Is absence of dynamic memory allocation highly recommended for such levels?
A: Static resource allocation is highly recommended for SIL 3/ASIL B and above, in addition to being a required directive in MISRA C. To make it possible for ACRN to be certified for a high safety integrity level, we consider static resource allocation mandatory, at least for releases to our customers who want to integrate ACRN in safety-critical use cases.
Q: There’re two option proposals for the implementation. Can an EPT find an address by VM id index and GPA?  A: If we want to support free page table when runtime, another input parameter ‘page table level’ may needs. If not, VM id index is enough.
Q: What’s performance impact on using large EPT page tables ? A: 2~4% performance gain in server platform. For RT VM, maybe use small page table. That depends the special runtime situation on the special hardware platform.
Q: If the performance gain to use large EPT page tables is not critical,  can we just simple the code not to merger the small dis-contiguous to a large EPT page table when runtime ? A: Let’s see. As the first step, we should remove the dynamic allocation to meet the FuSA’s requires. If  it’s performance critical then we would do it later. It would much easier to merge it after we implement the static memory allocation since it’s a contiguous array.
Q: How to configure the system memory if using static memory allocation ? A: ACRN is for IoT embedded system. The SW should be shipped along with HW. The configuration is fixed. And it will not apply to platform with the different hardware. For developer, you should use Kconfig to configure it by yourself.
Q: Will ACRN keep the error code in static memory allocation case  or keep dynamic allocation for open source release ? A: No, we could ASSERT the system  since it would never fail. As for whether needs to keep the dynamic allocation for open source release,  it’s an open to be closed.

  1. Next meeting agenda proposal:
 
WW Topic Presenter Status
WW21 ACRN roadmap introduction Ren, Jack Done
WW22 Patch submission process
ACRN feature list introduction
Wang, Hongbo
Ren, Jack
Done
WW23 Memory Management Chen, Jascon Done
WW24 Boot flow and fast boot Wu, Binbin Done
WW25 Memory Management Chen, Jason C Done
WW26 Audio virtualization Li, Jocelyn Done
WW27 Trusty Security on ACRN Zhu, Bing’s team Done
WW28 Clear Linux and use on ACRN Du, Alek Done
WW29 GVT-g for ACRN (a.k.a AcrnGT) Gong, Zhipeng Done
WW30 Device pass-through Zhai, Edwin Done
WW31 ACRN logical partition Ren, Jack/Xu, Anthony Done
WW32 ACRN interrupt management Chen, Jason Done
WW33 ACRN ACPI virtualization Edwin Zhai Done
WW34 ACRN S3/S5 management Fengwei Yin Done
WW35 ACRN P-state/C-state management Victor Sun Done
WW36 CPU Virtualization Jason Chen Done
WW37 Joint Design: VM Configuration Options Discussion Fengwei Yin Done
WW38 Joint Design: Remove dynamic memory allocation from ACRN memory management Li, Fei Today
WW39 IPU Sharing Bandi, Kushal Plan
WW40 USB virtualization Yu Wang Plan
WW41 ACRN VT-d Binbin Wu Plan
WW42 ACRN GPIO virtualization Yu Wang Plan
Slimboot Loader Introduction Plan
CPU Sharing (TBD)
ACRN real-time (TBD)
vSBL Introduction (TBD)
Open Source Android (TBD) Plan
 
Marketing/Events
  1. 2018 IoT solution world Congress
  1. Oct’18
  2. Status: demo submitted, waiting for acceptance
  1. 2019 Embedded World Exhibition & Conference
  1. Feb. 26-28, 2019
  2. CFP deadline: Aug. 31, 2018
  3. Nuremberg, Germany
Resources
  1. Project URL:
  1. Portal: https://projectacrn.org   
  2. Source code: https://github.com/projectacrn   
  3. email: info@...g
  4. Technical Mailing list: acrn-dev@...g
=============================
 
 
Best regards.
Hongbo
Tel: +86-21-6116 7445
MP: +86-1364 1793 689
 
 


FYI: Slim Boot Loader has Launched!

Wang, Hongbo
 

FYI.

SBL was announced as the OpenSource FW Conference 2018 in Erlangen, Germany.  If you go to the github link at https://github.com/slimbootloader you can find the source code and associated documentation.  Just below is the readme file from the URL.

 

 

 

 

 

Best regards.

Hongbo

Tel: +86-21-6116 7445

MP: +86-1364 1793 689

Mail: hongbo.wang@...

 


Re: How to pass through off-chip USB controller

Geoffroy Van Cutsem
 

Thanks Binbin!

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Wu, Binbin
Sent: Tuesday, September 11, 2018 7:47 AM
To: acrn-users@...
Cc: Tzeng, Tonny <tonny.tzeng@...>
Subject: Re: [acrn-users] How to pass through off-chip USB controller

Hi Geoffroy,

Yes, and the PR has been sent out.
https://github.com/projectacrn/acrn-hypervisor/pull/1210


On 9/10/2018 6:36 PM, Geoffroy Van Cutsem wrote:

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Wu, Binbin
Sent: Sunday, September 9, 2018 11:57 AM
To: acrn-users@...
Cc: Tzeng, Tonny <tonny.tzeng@...>
Subject: Re: [acrn-users] How to pass through off-chip USB controller

Hi Geoffroy,

Thanks for providing the info.
After checking the code, I did found a logic error when handling msix
table read/write in passthrough.
I have sent out a patch to fix the issue to
acrn-dev@... for review.
Thanks Binbin! I guess that's the one: https://lists.projectacrn.org/g/acrn-
dev/message/11368?

We will keep an eye on it (to see when it gets merged) and perhaps even
test it beforehand on our side if we get a chance!

Thanks,
Geoffroy

On 9/7/2018 9:50 PM, Geoffroy Van Cutsem wrote:
Hi Binbin, Edwin,

The error Tonny got at the time was with this combination (so not
the latest as of today):

- HV/DM: f815415

- SOS: Clear 24030 w/ 4.14.57-69 kernel

Looking it up on Github, this is the line you’re asking for:
https://github.com/projectacrn/acrn-hypervisor/blob/acrn-2018w30.4-1
40
000p/devicemodel/hw/pci/passthrough.c#L560

And yes, that’s the one you have below J

Thanks,

Geoffroy

*From:*acrn-users@...
[mailto:acrn-users@...] *On Behalf Of *Wu, Binbin
*Sent:* Friday, September 7, 2018 9:16 AM
*To:* acrn-users@...
*Subject:* Re: [acrn-users] How to pass through off-chip USB
controller

Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether
hw/pci/passthrough.c:560 is the line of code in bold?

static void

msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev
*ptdev,

uint64_t offset, int size, uint64_t data)

{

struct pci_vdev *dev;

struct msix_table_entry *entry;

uint8_t *dest8;

uint16_t *dest16;

uint32_t *dest32;

uint64_t *dest64;

size_t entry_offset;

uint32_t vector_control;

int index;

dev = ptdev->dev;

if (offset >= dev->msix.pba_offset &&

    offset < dev->msix.pba_offset + dev->msix.pba_size) {

switch (size) {

case 1:

dest8 = (uint8_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest8 = data;

break;

case 2:

dest16 = (uint16_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest16 = data;

break;

case 4:

dest32 = (uint32_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

**dest32 = data; *//is hw/pci/passthrough.c:560 this line of code?

break;

case 8:

dest64 = (uint64_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest64 = data;

break;

default:

break;

}

return;

}




Re: How to pass through off-chip USB controller

Wu, Binbin
 

Hi Geoffroy,

Yes, and the PR has been sent out.
https://github.com/projectacrn/acrn-hypervisor/pull/1210

On 9/10/2018 6:36 PM, Geoffroy Van Cutsem wrote:

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Wu, Binbin
Sent: Sunday, September 9, 2018 11:57 AM
To: acrn-users@...
Cc: Tzeng, Tonny <tonny.tzeng@...>
Subject: Re: [acrn-users] How to pass through off-chip USB controller

Hi Geoffroy,

Thanks for providing the info.
After checking the code, I did found a logic error when handling msix table
read/write in passthrough.
I have sent out a patch to fix the issue to acrn-dev@... for
review.
Thanks Binbin! I guess that's the one: https://lists.projectacrn.org/g/acrn-dev/message/11368?

We will keep an eye on it (to see when it gets merged) and perhaps even test it beforehand on our side if we get a chance!

Thanks,
Geoffroy

On 9/7/2018 9:50 PM, Geoffroy Van Cutsem wrote:
Hi Binbin, Edwin,

The error Tonny got at the time was with this combination (so not the
latest as of today):

- HV/DM: f815415

- SOS: Clear 24030 w/ 4.14.57-69 kernel

Looking it up on Github, this is the line you’re asking for:
https://github.com/projectacrn/acrn-hypervisor/blob/acrn-2018w30.4-140
000p/devicemodel/hw/pci/passthrough.c#L560

And yes, that’s the one you have below J

Thanks,

Geoffroy

*From:*acrn-users@...
[mailto:acrn-users@...] *On Behalf Of *Wu, Binbin
*Sent:* Friday, September 7, 2018 9:16 AM
*To:* acrn-users@...
*Subject:* Re: [acrn-users] How to pass through off-chip USB
controller

Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether
hw/pci/passthrough.c:560 is the line of code in bold?

static void

msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev
*ptdev,

uint64_t offset, int size, uint64_t data)

{

struct pci_vdev *dev;

struct msix_table_entry *entry;

uint8_t *dest8;

uint16_t *dest16;

uint32_t *dest32;

uint64_t *dest64;

size_t entry_offset;

uint32_t vector_control;

int index;

dev = ptdev->dev;

if (offset >= dev->msix.pba_offset &&

    offset < dev->msix.pba_offset + dev->msix.pba_size) {

switch (size) {

case 1:

dest8 = (uint8_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest8 = data;

break;

case 2:

dest16 = (uint16_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest16 = data;

break;

case 4:

dest32 = (uint32_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

**dest32 = data; *//is hw/pci/passthrough.c:560 this line of code?

break;

case 8:

dest64 = (uint64_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest64 = data;

break;

default:

break;

}

return;

}


Re: How to pass through off-chip USB controller

Geoffroy Van Cutsem
 

-----Original Message-----
From: acrn-users@... [mailto:acrn-
users@...] On Behalf Of Wu, Binbin
Sent: Sunday, September 9, 2018 11:57 AM
To: acrn-users@...
Cc: Tzeng, Tonny <tonny.tzeng@...>
Subject: Re: [acrn-users] How to pass through off-chip USB controller

Hi Geoffroy,

Thanks for providing the info.
After checking the code, I did found a logic error when handling msix table
read/write in passthrough.
I have sent out a patch to fix the issue to acrn-dev@... for
review.
Thanks Binbin! I guess that's the one: https://lists.projectacrn.org/g/acrn-dev/message/11368?

We will keep an eye on it (to see when it gets merged) and perhaps even test it beforehand on our side if we get a chance!

Thanks,
Geoffroy


On 9/7/2018 9:50 PM, Geoffroy Van Cutsem wrote:

Hi Binbin, Edwin,

The error Tonny got at the time was with this combination (so not the
latest as of today):

- HV/DM: f815415

- SOS: Clear 24030 w/ 4.14.57-69 kernel

Looking it up on Github, this is the line you’re asking for:
https://github.com/projectacrn/acrn-hypervisor/blob/acrn-2018w30.4-140
000p/devicemodel/hw/pci/passthrough.c#L560

And yes, that’s the one you have below J

Thanks,

Geoffroy

*From:*acrn-users@...
[mailto:acrn-users@...] *On Behalf Of *Wu, Binbin
*Sent:* Friday, September 7, 2018 9:16 AM
*To:* acrn-users@...
*Subject:* Re: [acrn-users] How to pass through off-chip USB
controller

Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether
hw/pci/passthrough.c:560 is the line of code in bold?

static void

msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev
*ptdev,

uint64_t offset, int size, uint64_t data)

{

struct pci_vdev *dev;

struct msix_table_entry *entry;

uint8_t *dest8;

uint16_t *dest16;

uint32_t *dest32;

uint64_t *dest64;

size_t entry_offset;

uint32_t vector_control;

int index;

dev = ptdev->dev;

if (offset >= dev->msix.pba_offset &&

    offset < dev->msix.pba_offset + dev->msix.pba_size) {

switch (size) {

case 1:

dest8 = (uint8_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest8 = data;

break;

case 2:

dest16 = (uint16_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest16 = data;

break;

case 4:

dest32 = (uint32_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

**dest32 = data; *//is hw/pci/passthrough.c:560 this line of code?

break;

case 8:

dest64 = (uint64_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest64 = data;

break;

default:

break;

}

return;

}



Re: How to pass through off-chip USB controller

Wu, Binbin
 

Hi Geoffroy,

Thanks for providing the info.
After checking the code, I did found a logic error when handling msix table read/write in passthrough.
I have sent out a patch to fix the issue to acrn-dev@... for review.

On 9/7/2018 9:50 PM, Geoffroy Van Cutsem wrote:

Hi Binbin, Edwin,

The error Tonny got at the time was with this combination (so not the latest as of today):

- HV/DM: f815415

- SOS: Clear 24030 w/ 4.14.57-69 kernel

Looking it up on Github, this is the line you’re asking for: https://github.com/projectacrn/acrn-hypervisor/blob/acrn-2018w30.4-140000p/devicemodel/hw/pci/passthrough.c#L560

And yes, that’s the one you have below J

Thanks,

Geoffroy

*From:*acrn-users@... [mailto:acrn-users@...] *On Behalf Of *Wu, Binbin
*Sent:* Friday, September 7, 2018 9:16 AM
*To:* acrn-users@...
*Subject:* Re: [acrn-users] How to pass through off-chip USB controller

Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether hw/pci/passthrough.c:560 is the line of code in bold?

static void

msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev *ptdev,

uint64_t offset, int size, uint64_t data)

{

struct pci_vdev *dev;

struct msix_table_entry *entry;

uint8_t *dest8;

uint16_t *dest16;

uint32_t *dest32;

uint64_t *dest64;

size_t entry_offset;

uint32_t vector_control;

int index;

dev = ptdev->dev;

if (offset >= dev->msix.pba_offset &&

    offset < dev->msix.pba_offset + dev->msix.pba_size) {

switch (size) {

case 1:

dest8 = (uint8_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest8 = data;

break;

case 2:

dest16 = (uint16_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest16 = data;

break;

case 4:

dest32 = (uint32_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

**dest32 = data; *//is hw/pci/passthrough.c:560 this line of code?

break;

case 8:

dest64 = (uint64_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest64 = data;

break;

default:

break;

}

return;

}


Re: How to pass through off-chip USB controller

Geoffroy Van Cutsem
 

Hi Binbin, Edwin,

 

The error Tonny got at the time was with this combination (so not the latest as of today):

- HV/DM: f815415

- SOS: Clear 24030 w/ 4.14.57-69 kernel

 

Looking it up on Github, this is the line you’re asking for: https://github.com/projectacrn/acrn-hypervisor/blob/acrn-2018w30.4-140000p/devicemodel/hw/pci/passthrough.c#L560

 

And yes, that’s the one you have below J

Thanks,

Geoffroy

 

From: acrn-users@... [mailto:acrn-users@...] On Behalf Of Wu, Binbin
Sent: Friday, September 7, 2018 9:16 AM
To: acrn-users@...
Subject: Re: [acrn-users] How to pass through off-chip USB controller

 

Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether hw/pci/passthrough.c:560 is the line of code in bold?

static void

msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev *ptdev,

uint64_t offset, int size, uint64_t data)

{

struct pci_vdev *dev;

struct msix_table_entry *entry;

uint8_t *dest8;

uint16_t *dest16;

uint32_t *dest32;

uint64_t *dest64;

size_t entry_offset;

uint32_t vector_control;

int index;

 

dev = ptdev->dev;

if (offset >= dev->msix.pba_offset &&

    offset < dev->msix.pba_offset + dev->msix.pba_size) {

switch (size) {

case 1:

dest8 = (uint8_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest8 = data;

break;

case 2:

dest16 = (uint16_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest16 = data;

break;

case 4:

dest32 = (uint32_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest32 = data;                //is hw/pci/passthrough.c:560 this line of code?

break;

case 8:

dest64 = (uint64_t *)(dev->msix.pba_page + offset -

    dev->msix.pba_page_offset);

*dest64 = data;

break;

default:

break;

}

return;

}

 


Re: How to pass through off-chip USB controller

Wu, Binbin
 

Hi Tonny,
Which version of your clearlinux SOS?
Is there any chance that can you confirm that whether hw/pci/passthrough.c:560 is the line of code in bold?

static void
msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_dev *ptdev,
uint64_t offset, int size, uint64_t data)
{
struct pci_vdev *dev;
struct msix_table_entry *entry;
uint8_t *dest8;
uint16_t *dest16;
uint32_t *dest32;
uint64_t *dest64;
size_t entry_offset;
uint32_t vector_control;
int index;
 
dev = ptdev->dev;
if (offset >= dev->msix.pba_offset &&
    offset < dev->msix.pba_offset + dev->msix.pba_size) {
switch (size) {
case 1:
dest8 = (uint8_t *)(dev->msix.pba_page + offset -
    dev->msix.pba_page_offset);
*dest8 = data;
break;
case 2:
dest16 = (uint16_t *)(dev->msix.pba_page + offset -
    dev->msix.pba_page_offset);
*dest16 = data;
break;
case 4:
dest32 = (uint32_t *)(dev->msix.pba_page + offset -
    dev->msix.pba_page_offset);
*dest32 = data;                //is hw/pci/passthrough.c:560 this line of code?
break;
case 8:
dest64 = (uint64_t *)(dev->msix.pba_page + offset -
    dev->msix.pba_page_offset);
*dest64 = data;
break;
default:
break;
}
return;
}
 


Re: How to pass through off-chip USB controller

Zhai, Edwin
 


Geoffroy,

Sorry, I seemed miss Tonny's reply.

From the lspci output from him, this controller support MSI-x, which probably trigger potential issue in ACRN side.


Geoffroy/Tonny,

Are you using the latest ACRN release? Do you have the source code of ACRN? If so, could you pls.  paste your code of ' hw/pci/passthrough.c:560' ?

Binbin,

Any potential issue for this MSI-x? I suspect this issue comes from invalid pointer access in MSI-x emulation code.

       Capabilities: [b0] MSI-X: Enable+ Count=8 Masked-

             Vector table: BAR=2 offset=00000000

             PBA: BAR=4 offset=00000000


The pci config of this dev from Tonny is:

01:00.0 USB controller: Fresco Logic FL1100 USB 3.0 Host Controller (rev 20) (prog-if 30 [XHCI])

       Subsystem: Fresco Logic FL1100 USB 3.0 Host Controller

       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+

       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

       Latency: 0, Cache Line Size: 64 bytes

       Interrupt: pin A routed to IRQ 22

       Region 0: Memory at 91500000 (64-bit, non-prefetchable) [size=64K]

       Region 2: Memory at 91511000 (64-bit, non-prefetchable) [size=4K]

       Region 4: Memory at 91510000 (64-bit, non-prefetchable) [size=4K]

       Capabilities: [40] Power Management version 3

             Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold+)

             Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

       Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+

             Address: 0000000000000000  Data: 0000

       Capabilities: [70] Express (v2) Endpoint, MSI 00

             DevCap:      MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us

                    ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 10.000W

             DevCtl:      CorrErr- NonFatalErr- FatalErr- UnsupReq-

                    RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+

                    MaxPayload 256 bytes, MaxReadReq 512 bytes

             DevSta:      CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-

             LnkCap:      Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 unlimited

                    ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-

             LnkCtl:      ASPM Disabled; RCB 64 bytes Disabled- CommClk+

                    ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

             LnkSta:      Speed 5GT/s (ok), Width x1 (ok)

                    TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

             DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported

                    AtomicOpsCap: 32bit- 64bit- 128bitCAS-

             DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled

                    AtomicOpsCtl: ReqEn-

             LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

                    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-

                    Compliance De-emphasis: -6dB

             LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-

                    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-

       Capabilities: [b0] MSI-X: Enable+ Count=8 Masked-

             Vector table: BAR=2 offset=00000000

             PBA: BAR=4 offset=00000000

       Capabilities: [100 v1] Advanced Error Reporting

             UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

             UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

             UESvrt:      DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-

             CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-

             CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+

             AERCap:      First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-

                    MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-

             HeaderLog: 00000000 00000000 00000000 00000000

       Kernel driver in use: xhci_hcd

       Kernel modules: xhci_pci
On 2018/9/6 20:47, Geoffroy Van Cutsem wrote:

Any update on this?

Thanks!

Geoffroy


-- 
Best Rgds,
Edwin

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