ACRN on CoffeeLake


Rajagopal Aravindan
 

Hello Victor,

W.r.t the subject, we were able to get ACRN to boot into SOS.
However, when trying  to start UOS we run into the below error

GVT: open /sys/kernel/gvt/control/create_gvt_instance failed
GVT: init failed
: No such file or directory
pci pci-gvt init failed

I guess its related to graphics virtualization but not able to get past that.

Any inputs on this, please ?

PFB (my signature) the board & sdc xmls.

Thanks,
Rajagopal

board.xml
<acrn-config board="acer">
	<BIOS_INFO>
	BIOS Information
	Vendor: Acer
	Version: P21-A1E
	Release Date: 04/12/2019
	BIOS Revision: 5.12
	</BIOS_INFO>

	<BASE_BOARD_INFO>
	Base Board Information
	Manufacturer: Acer
	Product Name: H310CH5-M23
	Version: P21-A1E
	</BASE_BOARD_INFO>

	<PCI_DEVICE>
	00:00.0 Host bridge: Intel Corporation 8th Gen Core Processor Host Bridge/DRAM Registers (rev 08)
	00:02.0 VGA compatible controller: Intel Corporation 8th Gen Core Processor Gaussian Mixture Model
	Region 0: Memory at de000000 (64-bit, non-prefetchable) [size=16M]
	Region 2: Memory at c0000000 (64-bit, prefetchable) [size=256M]
	00:08.0 System peripheral: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th Gen Core Processor Gaussian Mixture Model
	Region 0: Memory at df12f000 (64-bit, non-prefetchable) [disabled] [size=4K]
	00:14.0 USB controller: Intel Corporation 200 Series/Z370 Chipset Family USB 3.0 xHCI Controller
	Region 0: Memory at df110000 (64-bit, non-prefetchable) [size=64K]
	00:14.2 Signal processing controller: Intel Corporation 200 Series PCH Thermal Subsystem
	Region 0: Memory at df12e000 (64-bit, non-prefetchable) [size=4K]
	00:16.0 Communication controller: Intel Corporation 200 Series PCH CSME HECI #1
	Region 0: Memory at df12d000 (64-bit, non-prefetchable) [size=4K]
	00:17.0 SATA controller: Intel Corporation 200 Series PCH SATA controller [AHCI mode]
	Region 0: Memory at df128000 (32-bit, non-prefetchable) [size=8K]
	Region 1: Memory at df12c000 (32-bit, non-prefetchable) [size=256]
	Region 5: Memory at df12b000 (32-bit, non-prefetchable) [size=2K]
	00:1c.0 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5 (rev f0)
	00:1f.0 ISA bridge: Intel Corporation Device a2ca
	00:1f.2 Memory controller: Intel Corporation 200 Series/Z370 Chipset Family Power Management Controller
	Region 0: Memory at df124000 (32-bit, non-prefetchable) [disabled] [size=16K]
	00:1f.3 Audio device: Intel Corporation 200 Series PCH HD Audio
	Region 0: Memory at df120000 (64-bit, non-prefetchable) [size=16K]
	Region 4: Memory at df100000 (64-bit, non-prefetchable) [size=64K]
	00:1f.4 SMBus: Intel Corporation 200 Series/Z370 Chipset Family SMBus Controller
	Region 0: Memory at df12a000 (64-bit, non-prefetchable) [size=256]
	01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)
	Region 2: Memory at df004000 (64-bit, non-prefetchable) [size=4K]
	Region 4: Memory at df000000 (64-bit, non-prefetchable) [size=16K]
	</PCI_DEVICE>

	<PCI_VID_PID>
	00:00.0 0600: 8086:3e1f (rev 08)
	00:02.0 0300: 8086:3e91
	00:08.0 0880: 8086:1911
	00:14.0 0c03: 8086:a2af
	00:14.2 1180: 8086:a2b1
	00:16.0 0780: 8086:a2ba
	00:17.0 0106: 8086:a282
	00:1c.0 0604: 8086:a294 (rev f0)
	00:1f.0 0601: 8086:a2ca
	00:1f.2 0580: 8086:a2a1
	00:1f.3 0403: 8086:a2f0
	00:1f.4 0c05: 8086:a2a3
	01:00.0 0200: 10ec:8168 (rev 15)
	</PCI_VID_PID>

	<WAKE_VECTOR_INFO>
	#define WAKE_VECTOR_32          0xB65B0F0CUL
	#define WAKE_VECTOR_64          0xB65B0F18UL
	</WAKE_VECTOR_INFO>

	<RESET_REGISTER_INFO>
	#define RESET_REGISTER_ADDRESS  0xCF9UL
	#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
	#define RESET_REGISTER_VALUE    0x6U
	</RESET_REGISTER_INFO>

	<PM_INFO>
	#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_EVT_BIT_WIDTH      0x20U
	#define PM1A_EVT_BIT_OFFSET     0x0U
	#define PM1A_EVT_ADDRESS        0x1800UL
	#define PM1A_EVT_ACCESS_SIZE    0x2U
	#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_EVT_BIT_WIDTH      0x0U
	#define PM1B_EVT_BIT_OFFSET     0x0U
	#define PM1B_EVT_ADDRESS        0x0UL
	#define PM1B_EVT_ACCESS_SIZE    0x2U
	#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1A_CNT_BIT_WIDTH      0x10U
	#define PM1A_CNT_BIT_OFFSET     0x0U
	#define PM1A_CNT_ADDRESS        0x1804UL
	#define PM1A_CNT_ACCESS_SIZE    0x2U
	#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
	#define PM1B_CNT_BIT_WIDTH      0x0U
	#define PM1B_CNT_BIT_OFFSET     0x0U
	#define PM1B_CNT_ADDRESS        0x0UL
	#define PM1B_CNT_ACCESS_SIZE    0x2U
	</PM_INFO>

	<S3_INFO>
	#define S3_PKG_VAL_PM1A         0x5U
	#define S3_PKG_VAL_PM1B         0U
	#define S3_PKG_RESERVED         0x0U
	</S3_INFO>

	<S5_INFO>
	#define S5_PKG_VAL_PM1A         0x7U
	#define S5_PKG_VAL_PM1B         0U
	#define S5_PKG_RESERVED         0x0U
	</S5_INFO>

	<DRHD_INFO>
	#define DRHD_COUNT              2U

	#define DRHD0_DEV_CNT           0x1U
	#define DRHD0_SEGMENT           0x0U
	#define DRHD0_FLAGS             0x0U
	#define DRHD0_REG_BASE          0xFED90000UL
	#define DRHD0_IGNORE            true
	#define DRHD0_DEVSCOPE0_TYPE    0x1U
	#define DRHD0_DEVSCOPE0_ID      0x0U
	#define DRHD0_DEVSCOPE0_BUS     0x0U
	#define DRHD0_DEVSCOPE0_PATH    0x10U

	#define DRHD1_DEV_CNT           0x2U
	#define DRHD1_SEGMENT           0x0U
	#define DRHD1_FLAGS             0x1U
	#define DRHD1_REG_BASE          0xFED91000UL
	#define DRHD1_IGNORE            false
	#define DRHD1_DEVSCOPE0_TYPE    0x3U
	#define DRHD1_DEVSCOPE0_ID      0x2U
	#define DRHD1_DEVSCOPE0_BUS     0xf0U
	#define DRHD1_DEVSCOPE0_PATH    0xf8U
	#define DRHD1_DEVSCOPE1_TYPE    0x4U
	#define DRHD1_DEVSCOPE1_ID      0x0U
	#define DRHD1_DEVSCOPE1_BUS     0x0U
	#define DRHD1_DEVSCOPE1_PATH    0xf8U

	</DRHD_INFO>

	<CPU_BRAND>
	"Intel(R) Core(TM) i3-8100 CPU @ 3.60GHz"
	</CPU_BRAND>

	<CX_INFO>
	{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U},	/* C1 */
	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x97U, 0x00U},	/* C2 */
	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U},	/* C3 */
	</CX_INFO>

	<PX_INFO>
	{0xE10UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002400UL, 0x002400UL},	/* P0 */
	{0xD48UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002200UL, 0x002200UL},	/* P1 */
	{0xC80UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002000UL, 0x002000UL},	/* P2 */
	{0xBB8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001E00UL, 0x001E00UL},	/* P3 */
	{0xB54UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001D00UL, 0x001D00UL},	/* P4 */
	{0xA8CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001B00UL, 0x001B00UL},	/* P5 */
	{0x9C4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001900UL, 0x001900UL},	/* P6 */
	{0x8FCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL},	/* P7 */
	{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL},	/* P8 */
	{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL},	/* P9 */
	{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL},	/* P10 */
	{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL},	/* P11 */
	{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL},	/* P12 */
	{0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL},	/* P13 */
	{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL},	/* P14 */
	{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL},	/* P15 */
	</PX_INFO>

	<CLOS_INFO>
	clos supported by cache:False
	clos max:0
	</CLOS_INFO>

	<SYSTEM_RAM_INFO>
	00001000-00057fff : System RAM
	00059000-0009dfff : System RAM
	00100000-3fffffff : System RAM
	40400000-ae6bafff : System RAM
	ae6bd000-b58b7fff : System RAM
	b6540000-b6549fff : System RAM
	b6ffe000-b6ffefff : System RAM
	100000000-23effffff : System RAM
	</SYSTEM_RAM_INFO>

	<BLOCK_DEVICE_INFO>
	/dev/sda3: TYPE="ext4"
	/dev/sda4: TYPE="ext4"
	</BLOCK_DEVICE_INFO>

	<TTYS_INFO>
	seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
	</TTYS_INFO>

	<AVAILABLE_IRQ_INFO>
	3, 5, 6, 7, 10, 11, 12, 13, 14, 15
	</AVAILABLE_IRQ_INFO>

	<TOTAL_MEM_INFO>
	7975552 kB
	</TOTAL_MEM_INFO>

	<CPU_PROCESSOR_INFO>
	0, 1, 2, 3
	</CPU_PROCESSOR_INFO>

</acrn-config>

sdc.xml
<?xml version='1.0' encoding='utf-8'?>
<acrn-config board="acer" scenario="sdc">
    <vm id="0">
        <load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">SOS_VM</load_order>
        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
        <uuid configurable="0" desc="vm uuid">dbbbd434-7a57-4216-a12c-2201f1ab0240</uuid>
        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
            <guest_flag>GUEST_FLAG_HIGHEST_SEVERITY</guest_flag>
        </guest_flags>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution." />
        <memory>
            <start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
            <size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
        </memory>
        <os_config>
            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
            <bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
        </os_config>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." readonly="true">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
        </vuart>
        <pci_dev_num configurable="0" desc="pci devices number">SOS_EMULATED_PCI_DEV_NUM</pci_dev_num>
        <pci_devs configurable="0" desc="pci devices list">sos_pci_devs</pci_devs>
        <board_private>
            <rootfs desc="rootfs for Linux kernel">/dev/sda3</rootfs>
            <console desc="ttyS console for Linux kernel">/dev/ttyS0</console>
            <bootargs desc="Specify kernel boot arguments">        rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
        i915.nuclear_pageflip=1 i915.avail_planes_per_pipe=0x01010F i915.domain_plane_owners=0x011111110000 i915.enable_gvt=1
        </bootargs>
        </board_private>
    </vm>
    <vm id="1">
        <load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">POST_LAUNCHED_VM</load_order>
        <uuid configurable="0" desc="vm uuid">d2795438-25d6-11e8-864e-cb7a18b34643</uuid>
        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
            <guest_flag />
        </guest_flags>
        <vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
            <pcpu_id>1</pcpu_id>
            <pcpu_id>2</pcpu_id>
            <pcpu_id>3</pcpu_id>
        </vcpu_affinity>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution." />
        <epc_section desc="epc section">
            <base desc="SGX EPC section base, must be page aligned">0</base>
            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
        </epc_section>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." >INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base> 
            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
        </vuart>
    </vm>
    <vm configurable="0" desc="specific for Kata" id="2">
        <load_order configurable="0" desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM.">POST_LAUNCHED_VM</load_order>
        <uuid configurable="0" desc="vm uuid">a7ada506-1ab0-4b6b-a0da-e513ca9b8c2f</uuid>
        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
        <vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
            <pcpu_id>3</pcpu_id>
        </vcpu_affinity>
        <epc_section desc="epc section">
            <base desc="SGX EPC section base, must be page aligned">0</base>
            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
        </epc_section>
        <vuart id="0">
            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
            <base configurable="0" desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM1 irq">COM1_BASE</irq>
        </vuart>
        <vuart id="1">
            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
            <base configurable="0" desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
            <irq configurable="0" desc="vCOM2 irq">COM2_BASE</irq>
            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
        </vuart>
    </vm>
</acrn-config>
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