Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Rajagopal Aravindan

Hello Victor,

>>Could you please share your board xml file?
PFB (my signature) the board xml.


<acrn-config board="lenl450">
BIOS Information
Vendor: LENOVO
Version: JDET55WW (1.17 )
Release Date: 11/20/2015
BIOS Revision: 1.17

Base Board Information
Manufacturer: LENOVO
Product Name: Intel powered classmate PC
Version: SDK0E50510 WIN

00:00.0 Host bridge: Intel Corporation Broadwell-U Host Bridge -OPI (rev 09)
00:02.0 VGA compatible controller: Intel Corporation HD Graphics 5500 (rev 09)
Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at c0000000 (64-bit, prefetchable) [size=512M]
00:03.0 Audio device: Intel Corporation Broadwell-U Audio Controller (rev 09)
Region 0: Memory at e1230000 (64-bit, non-prefetchable) [size=16K]
00:14.0 USB controller: Intel Corporation Wildcat Point-LP USB xHCI Controller (rev 03)
Region 0: Memory at e1220000 (64-bit, non-prefetchable) [size=64K]
00:16.0 Communication controller: Intel Corporation Wildcat Point-LP MEI Controller #1 (rev 03)
Region 0: Memory at e1239000 (64-bit, non-prefetchable) [size=32]
00:19.0 Ethernet controller: Intel Corporation Ethernet Connection (3) I218-LM (rev 03)
Region 0: Memory at e1200000 (32-bit, non-prefetchable) [size=128K]
Region 1: Memory at e123e000 (32-bit, non-prefetchable) [size=4K]
00:1b.0 Audio device: Intel Corporation Wildcat Point-LP High Definition Audio Controller (rev 03)
Region 0: Memory at e1234000 (64-bit, non-prefetchable) [size=16K]
00:1c.0 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #1 (rev e3)
00:1c.2 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #3 (rev e3)
00:1c.5 PCI bridge: Intel Corporation Wildcat Point-LP PCI Express Root Port #6 (rev e3)
00:1d.0 USB controller: Intel Corporation Wildcat Point-LP USB EHCI Controller (rev 03)
Region 0: Memory at e123d000 (32-bit, non-prefetchable) [size=1K]
00:1f.0 ISA bridge: Intel Corporation Wildcat Point-LP LPC Controller (rev 03)
00:1f.2 SATA controller: Intel Corporation Wildcat Point-LP SATA Controller [AHCI Mode] (rev 03)
Region 5: Memory at e123c000 (32-bit, non-prefetchable) [size=2K]
00:1f.3 SMBus: Intel Corporation Wildcat Point-LP SMBus Controller (rev 03)
Region 0: Memory at e1238000 (64-bit, non-prefetchable) [size=256]
00:1f.6 Signal processing controller: Intel Corporation Wildcat Point-LP Thermal Management Controller (rev 03)
Region 0: Memory at e123b000 (64-bit, non-prefetchable) [size=4K]
04:00.0 Network controller: Intel Corporation Wireless 7265 (rev 61)
Region 0: Memory at e1100000 (64-bit, non-prefetchable) [size=8K]
05:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTS5227 PCI Express Card Reader (rev 01)
Region 0: Memory at e1000000 (32-bit, non-prefetchable) [size=4K]

00:00.0 0600: 8086:1604 (rev 09)
00:02.0 0300: 8086:1616 (rev 09)
00:03.0 0403: 8086:160c (rev 09)
00:14.0 0c03: 8086:9cb1 (rev 03)
00:16.0 0780: 8086:9cba (rev 03)
00:19.0 0200: 8086:15a2 (rev 03)
00:1b.0 0403: 8086:9ca0 (rev 03)
00:1c.0 0604: 8086:9c90 (rev e3)
00:1c.2 0604: 8086:9c94 (rev e3)
00:1c.5 0604: 8086:9c9a (rev e3)
00:1d.0 0c03: 8086:9ca6 (rev 03)
00:1f.0 0601: 8086:9cc3 (rev 03)
00:1f.2 0106: 8086:9c83 (rev 03)
00:1f.3 0c05: 8086:9ca2 (rev 03)
00:1f.6 1180: 8086:9ca4 (rev 03)
04:00.0 0280: 8086:095b (rev 61)
05:00.0 ff00: 10ec:5227 (rev 01)

#define WAKE_VECTOR_32          0xACF6800CUL
#define WAKE_VECTOR_64          0xACF68018UL


#define PM1A_EVT_BIT_WIDTH      0x20U
#define PM1A_EVT_BIT_OFFSET     0x0U
#define PM1A_EVT_ADDRESS        0x1800UL
#define PM1A_EVT_ACCESS_SIZE    0x2U
#define PM1B_EVT_BIT_WIDTH      0x0U
#define PM1B_EVT_BIT_OFFSET     0x0U
#define PM1B_EVT_ADDRESS        0x0UL
#define PM1B_EVT_ACCESS_SIZE    0x2U
#define PM1A_CNT_BIT_WIDTH      0x10U
#define PM1A_CNT_BIT_OFFSET     0x0U
#define PM1A_CNT_ADDRESS        0x1804UL
#define PM1A_CNT_ACCESS_SIZE    0x2U
#define PM1B_CNT_BIT_WIDTH      0x0U
#define PM1B_CNT_BIT_OFFSET     0x0U
#define PM1B_CNT_ADDRESS        0x0UL
#define PM1B_CNT_ACCESS_SIZE    0x2U



#define DRHD_COUNT              2U

#define DRHD0_DEV_CNT           0x1U
#define DRHD0_SEGMENT           0x0U
#define DRHD0_FLAGS             0x0U
#define DRHD0_REG_BASE          0xFED90000UL
#define DRHD0_IGNORE            true
#define DRHD0_DEVSCOPE0_TYPE    0x1U
#define DRHD0_DEVSCOPE0_ID      0x0U
#define DRHD0_DEVSCOPE0_BUS     0x0U
#define DRHD0_DEVSCOPE0_PATH    0x10U

#define DRHD1_DEV_CNT           0x2U
#define DRHD1_SEGMENT           0x0U
#define DRHD1_FLAGS             0x1U
#define DRHD1_REG_BASE          0xFED91000UL
#define DRHD1_IGNORE            false
#define DRHD1_DEVSCOPE0_TYPE    0x3U
#define DRHD1_DEVSCOPE0_ID      0x2U
#define DRHD1_DEVSCOPE0_BUS     0xf0U
#define DRHD1_DEVSCOPE0_PATH    0xf8U
#define DRHD1_DEVSCOPE1_TYPE    0x4U
#define DRHD1_DEVSCOPE1_ID      0x0U
#define DRHD1_DEVSCOPE1_BUS     0xf0U
#define DRHD1_DEVSCOPE1_PATH    0x78U


"Intel(R) Core(TM) i5-5300U CPU @ 2.30GHz"

/* Cx data is not available */

{0x8FDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001D00UL, 0x001D00UL}, /* P0 */
{0x8FCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL}, /* P1 */
{0x898UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001600UL, 0x001600UL}, /* P2 */
{0x7D0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001400UL, 0x001400UL}, /* P3 */
{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P4 */
{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P5 */
{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P6 */
{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P7 */
{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P8 */
{0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */
{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P10 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P11 */
{0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P12 */
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P13 */
{0x258UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000600UL, 0x000600UL}, /* P14 */
{0x1F4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000500UL, 0x000500UL}, /* P15 */

clos supported by cache:False
clos max:0


00001000-00057fff : System RAM
00059000-0008bfff : System RAM
00100000-a9efdfff : System RAM
acfff000-acffffff : System RAM
100000000-24dffffff : System RAM

/dev/sda6: TYPE="ext4"
/dev/sda7: TYPE="ext4"
/dev/sda8: TYPE="ext4"

3, 4, 5, 6, 7, 10, 11, 13, 14, 15

8032796 kB

0, 1, 2, 3


From: acrn-users@... <acrn-users@...> on behalf of Victor Sun <victor.sun@...>
Sent: Saturday, November 16, 2019 7:50 AM
To: acrn-users@... <acrn-users@...>
Subject: Re: [acrn-dev] [acrn-users] ACRN on ThinkPad-L450 laptop

Hi Rajagopal,

Could you please share your board xml file?

If there is no UART in your laptop, ACRN should be OK to run if no configuration conflict but it is hard to debug when issue happens.

On 11/15/2019 11:33 PM, a.rajagopal via Lists.Projectacrn.Org wrote:
Hello Victor,

>>Make sure your code include below commit:

>>commit cdd086a81d5997d52ace5a541c9b1e99ce35c24c

With the above commit, I run into the below error ...

..../", line 339, in parser_vuart_console


    if ttys and 'BDF' in ttys[0] or '/dev' in ttys[0]:

TypeError: argument of type 'NoneType' is not iterable

My laptop doesn't have RS232/DB9 port, is it mandatory or how to skip ?


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