Hi, for CAT support (L2/L3), you can check it by cpuid;

For L2, if on core platform it is private for a physical core,  L3/LLC is shared between cores, if hyper-threading is not enabled, L2 CAT not helpful.

L2/L3 CAT use different MSR to set, so no matter the cache ways the same or not.

You can refer ACRN: release_2.5 branch, the tgl-rvp board industry scenario has L3 CAT setting.