Re: question regarding acrn-hypervisor vioapic implementation


Yin, Fengwei <fengwei.yin@...>
 

This change update the interrupt from edge triggered to low level
triggered. Which is unusual case.

Is it possible that this is related with workaround in linux kernel
ioapic for version 0x11?

Regards
Yin, Fengwei

On 7/1/2018 8:27 PM, Chen, Jason CJ wrote:
Ok, it does one case that we don’t take care – the update is done during the interrupt is unmasked. Let’s figure out one solution for this.
Thanks & Best Regards,
Jason Chen
SSG -> OTC -> Intel Auto Hypervisor Team
*From:*acrn-users@... [mailto:acrn-users@...] *On Behalf Of *Xu, Anthony
*Sent:* Saturday, June 30, 2018 6:12 AM
*To:* acrn-users@...
*Subject:* Re: [acrn-users] question regarding acrn-hypervisor vioapic implementation
Jason/Fengwei,
Our assumption is not correct.
HV needs to handle RTL change even when it is unmasked.
Anthony
*From:*acrn-users@... <mailto:acrn-users@...> [mailto:acrn-users@...] *On Behalf Of *Abdul
*Sent:* Friday, June 29, 2018 5:42 AM
*To:* acrn-users@... <mailto:acrn-users@...>
*Subject:* Re: [acrn-users] question regarding acrn-hypervisor vioapic implementation
Hi Anthony,
I am using sos kernel from https://github.com/projectacrn/acrn-kernel/commits/master commit-id: 9bba4539d654af06d4642f9773e5444da7ee055d and the kernel_config_sos present in the same repository.
Platform: Apollo Lake
I can observe that vioapic RTL is updated for IRQ - 14 but the physical ioapic RTL is not updated
Logs:
/ACRN:\>vioapic 0/
/PIN     VEC     DM      DEST    TM      DELM    IRR     MASK/
/14      0x3E    logic   0x1     level   1       0       0/
/ACRN:\>dump_ioapic/
/IRQ     PIN     RTE.HI32        RTE.LO32        VEC     DST     DM     TM      DELM    IRR     MASK/
/014     014     0x01000000      0x0000098E      0x8E    0x01 logic   edge    1       0       0/
This IRQ corresponds to device INT3452
Logs:
/root@:Dom0 ~ $ cat /proc/interrupts /
/            CPU0 /
/  14:          0   IO-APIC   14-fasteoi   INT3452:00, INT3452:01,
INT3452:02, INT3452:03/
As a result sos is not receiving interrupts from the device.
I dumped the ioapic writes and saw that RTL was being updated while the interrupt was unmasked
Logs:
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry 10000/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry 10000/
/[cpu=0][sev=3]:vioapic: ioapic pin14: recalculate vlapic
trigger-mode reg/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry 10000/
/[cpu=0][sev=3]:vioapic: ioapic pin14: recalculate vlapic
trigger-mode reg/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry93e /
/[cpu=0][sev=3]:vioapic: ioapic pin14: recalculate vlapic
trigger-mode reg/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry 93e/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry a93e                        ----->   Update is made while the interrupt
is unmasked/
/[cpu=0][sev=3]:vioapic: ioapic pin14: recalculate vlapic
trigger-mode reg/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry a93e/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry a93e/
/[cpu=0][sev=3]:vioapic: ioapic pin14: redir table entry a93e/
Thanks!
Best Regards,
Abdul

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