[PATCH 0/3] HV: vCPI: fix pass-thru pcie device may access MSI-X BAR


Li, Fei1
 

The serial fix pass-thru pcie device may access MSI-X BAR besides MSI-X Table Structure.

Fei Li (3):
hv:io: wrap mmio read/write
hv: pci: use mmio_read/write directly
hv: vpci: fix pass-thru pcie device may access MSI-X BAR

hypervisor/dm/vpci/vmsix.c | 51 ++++++++++++++++++----------
hypervisor/hw/pci.c | 29 ++--------------
hypervisor/include/arch/x86/asm/io.h | 38 +++++++++++++++++++++
3 files changed, 74 insertions(+), 44 deletions(-)

--
2.34.1


Eddie Dong
 

-----Original Message-----
From: Li, Fei1 <fei1.li@...>
Sent: Tuesday, October 18, 2022 11:20 PM
To: acrn-dev@...
Cc: Dong, Eddie <eddie.dong@...>; Huang, Yonghua
<yonghua.huang@...>; Chen, Jason CJ <jason.cj.chen@...>
Subject: [PATCH 0/3] HV: vCPI: fix pass-thru pcie device may access MSI-X BAR

The serial fix pass-thru pcie device may access MSI-X BAR besides MSI-X Table
... may access registers other than MSI-X table registers in the same BAR, which is trapped by ACRN as a whole.
MSI-X table registers are emulated/remapped, while other registers should be passed thru.


This is what you mean, right?
Structure.

Fei Li (3):
hv:io: wrap mmio read/write
hv: pci: use mmio_read/write directly
hv: vpci: fix pass-thru pcie device may access MSI-X BAR

hypervisor/dm/vpci/vmsix.c | 51 ++++++++++++++++++----------
hypervisor/hw/pci.c | 29 ++--------------
hypervisor/include/arch/x86/asm/io.h | 38 +++++++++++++++++++++
3 files changed, 74 insertions(+), 44 deletions(-)

--
2.34.1


Li, Fei1
 

On 2022-10-20 at 01:12:18 +0800, Dong, Eddie wrote:


-----Original Message-----
From: Li, Fei1 <fei1.li@...>
Sent: Tuesday, October 18, 2022 11:20 PM
To: acrn-dev@...
Cc: Dong, Eddie <eddie.dong@...>; Huang, Yonghua
<yonghua.huang@...>; Chen, Jason CJ <jason.cj.chen@...>
Subject: [PATCH 0/3] HV: vCPI: fix pass-thru pcie device may access MSI-X BAR

The serial fix pass-thru pcie device may access MSI-X BAR besides MSI-X Table
... may access registers other than MSI-X table registers in the same BAR, which is trapped by ACRN as a whole.
MSI-X table registers are emulated/remapped, while other registers should be passed thru.


This is what you mean, right?
yes
Structure.

Fei Li (3):
hv:io: wrap mmio read/write
hv: pci: use mmio_read/write directly
hv: vpci: fix pass-thru pcie device may access MSI-X BAR

hypervisor/dm/vpci/vmsix.c | 51 ++++++++++++++++++----------
hypervisor/hw/pci.c | 29 ++--------------
hypervisor/include/arch/x86/asm/io.h | 38 +++++++++++++++++++++
3 files changed, 74 insertions(+), 44 deletions(-)

--
2.34.1