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[PATCH 0/3] Add Timed GPIO passthrough
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chenli.wei
From: Chenli Wei <chenli.wei@...>
This series patches add Timed GPIO passthrough feature for post-launched VM. 1 HV patch, add a handler to process the Timed GPIO register. 2 DM patch, add a parameter and create ACPI table for post-launched VM. 3 Misc patch, add an element for user to enable or disable the Timed GPIO passthrough. Chenli Wei (3): hv: add Timed GPIO process handler misc: add element to config Timed GPIO dm: add Timed GPIO parameter devicemodel/Makefile | 1 + devicemodel/core/main.c | 7 ++ devicemodel/hw/platform/acpi/acpi.c | 4 + devicemodel/hw/platform/tgpio.c | 82 ++++++++++++++++++ devicemodel/include/tgpio.h | 24 ++++++ hypervisor/Makefile | 1 + hypervisor/arch/x86/guest/vm.c | 4 + hypervisor/dm/vtgpio.c | 84 +++++++++++++++++++ hypervisor/include/arch/x86/asm/vm_config.h | 2 + hypervisor/include/dm/vtgpio.h | 12 +++ misc/config_tools/schema/config.xsd | 5 ++ .../xforms/vm_configurations.c.xsl | 13 +++ 12 files changed, 239 insertions(+) create mode 100644 devicemodel/hw/platform/tgpio.c create mode 100644 devicemodel/include/tgpio.h create mode 100644 hypervisor/dm/vtgpio.c create mode 100644 hypervisor/include/dm/vtgpio.h -- 2.25.1
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Junjie Mao
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-----Original Message-----It is recommended to describe the background of Timed GPIO, why it is needed, what is the major challenges to tackle with and how this patch series is designed. Also is this series still in the POC stage (which means it works for evaluation but requires further refinement for generality)? That should be explicitly stated as well in the cover letter. --- Best Regards Junjie Mao
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Traditionally, we support passthru of PCIe devices. Later on, we added the capability to passthru certain range of MMIO registers to a guest in the granularity of 4KB.
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It seems this patch want to add the capability of passthru certain MMIO registers without at the granularity of 4KB. In this case, I have questions how we can handle the other registers inside same 4KB page? I assume we should let SOS VM handle them. I didn't see this in this patch. Secondary, I am wondering the need of this capability. Let the DM of SOS VM to handle the GPIO registers is much clean, though slower. But I thought the performance issue is not the focus here. If we really want to passthru part MMIo registers to a VM, we need to 1) make sure the entire 4KB pages are owned by SOS VM initially, 2) the assignment should come from SOS VM, not pre-configuration, 3) No any interrupt, nor DMA --- Question: how can we check this? Eddie
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