[PATCH 1/1] hv: fix read/write some debug MSRs without #GP received #gp


Jiang
 

Some debug MSRs are unsupported in hypervisor, when read/write these MSRs, hypervisor do not intercept it. This patch add connected MSRs into unsupported_msrs array, hypervisor will intercept debug MSRs and inject #GP to guest.

Tracked-On: #3569
Signed-off-by: Jiang Mao<maox.jiang@intel.com>
---
hypervisor/arch/x86/guest/vmsr.c | 73 ++++++++++++++++++++++++++++++-
hypervisor/include/arch/x86/msr.h | 73 +++++++++++++++++++++++++++----
2 files changed, 136 insertions(+), 10 deletions(-)

diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index 26acd703..8202e648 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -78,7 +78,7 @@ static const uint32_t mtrr_msrs[NUM_MTRR_MSRS] = {
};

/* Following MSRs are intercepted, but it throws GPs for any guest accesses */
-#define NUM_UNSUPPORTED_MSRS 99U
+#define NUM_UNSUPPORTED_MSRS 168U
static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
/* Variable MTRRs are not supported */
MSR_IA32_MTRR_PHYSBASE_0,
@@ -201,6 +201,77 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {

/* Performance Monitoring: CPUID.01H.ECX[15] X86_FEATURE_PDCM */
MSR_IA32_PERF_CAPABILITIES,
+ MSR_IA32_DEBUGCTL,
+
+ /* Last Branch Record (LBR) Stack disabled */
+ MSR_LBR_SELECT,
+ MSR_LER_TO_LIP,
+ MSR_LER_FROM_LIP,
+ MSR_LASTBRANCH_TOS,
+ MSR_LASTBRANCH_0_FROM_IP,
+ MSR_LASTBRANCH_1_FROM_IP,
+ MSR_LASTBRANCH_2_FROM_IP,
+ MSR_LASTBRANCH_3_FROM_IP,
+ MSR_LASTBRANCH_4_FROM_IP,
+ MSR_LASTBRANCH_5_FROM_IP,
+ MSR_LASTBRANCH_6_FROM_IP,
+ MSR_LASTBRANCH_7_FROM_IP,
+ MSR_LASTBRANCH_8_FROM_IP,
+ MSR_LASTBRANCH_9_FROM_IP,
+ MSR_LASTBRANCH_10_FROM_IP,
+ MSR_LASTBRANCH_11_FROM_IP,
+ MSR_LASTBRANCH_12_FROM_IP,
+ MSR_LASTBRANCH_13_FROM_IP,
+ MSR_LASTBRANCH_14_FROM_IP,
+ MSR_LASTBRANCH_15_FROM_IP,
+ MSR_LASTBRANCH_16_FROM_IP,
+ MSR_LASTBRANCH_17_FROM_IP,
+ MSR_LASTBRANCH_18_FROM_IP,
+ MSR_LASTBRANCH_19_FROM_IP,
+ MSR_LASTBRANCH_20_FROM_IP,
+ MSR_LASTBRANCH_21_FROM_IP,
+ MSR_LASTBRANCH_22_FROM_IP,
+ MSR_LASTBRANCH_23_FROM_IP,
+ MSR_LASTBRANCH_24_FROM_IP,
+ MSR_LASTBRANCH_25_FROM_IP,
+ MSR_LASTBRANCH_26_FROM_IP,
+ MSR_LASTBRANCH_27_FROM_IP,
+ MSR_LASTBRANCH_28_FROM_IP,
+ MSR_LASTBRANCH_29_FROM_IP,
+ MSR_LASTBRANCH_30_FROM_IP,
+ MSR_LASTBRANCH_31_FROM_IP,
+ MSR_LASTBRANCH_0_TO_IP,
+ MSR_LASTBRANCH_1_TO_IP,
+ MSR_LASTBRANCH_2_TO_IP,
+ MSR_LASTBRANCH_3_TO_IP,
+ MSR_LASTBRANCH_4_TO_IP,
+ MSR_LASTBRANCH_5_TO_IP,
+ MSR_LASTBRANCH_6_TO_IP,
+ MSR_LASTBRANCH_7_TO_IP,
+ MSR_LASTBRANCH_8_TO_IP,
+ MSR_LASTBRANCH_9_TO_IP,
+ MSR_LASTBRANCH_10_TO_IP,
+ MSR_LASTBRANCH_11_TO_IP,
+ MSR_LASTBRANCH_12_TO_IP,
+ MSR_LASTBRANCH_13_TO_IP,
+ MSR_LASTBRANCH_14_TO_IP,
+ MSR_LASTBRANCH_15_TO_IP,
+ MSR_LASTBRANCH_16_TO_IP,
+ MSR_LASTBRANCH_17_TO_IP,
+ MSR_LASTBRANCH_18_TO_IP,
+ MSR_LASTBRANCH_19_TO_IP,
+ MSR_LASTBRANCH_20_TO_IP,
+ MSR_LASTBRANCH_21_TO_IP,
+ MSR_LASTBRANCH_22_TO_IP,
+ MSR_LASTBRANCH_23_TO_IP,
+ MSR_LASTBRANCH_24_TO_IP,
+ MSR_LASTBRANCH_25_TO_IP,
+ MSR_LASTBRANCH_26_TO_IP,
+ MSR_LASTBRANCH_27_TO_IP,
+ MSR_LASTBRANCH_28_TO_IP,
+ MSR_LASTBRANCH_29_TO_IP,
+ MSR_LASTBRANCH_30_TO_IP,
+ MSR_LASTBRANCH_31_TO_IP,

/* Debug Store disabled: CPUID.01H.EDX[21] X86_FEATURE_DTES */
MSR_IA32_DS_AREA,
diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h
index 1eea6a1a..660fe500 100644
--- a/hypervisor/include/arch/x86/msr.h
+++ b/hypervisor/include/arch/x86/msr.h
@@ -361,14 +361,6 @@
#define MSR_EBC_FREQUENCY_ID 0x0000002CU
#define MSR_SMI_COUNT 0x00000034U
#define MSR_CORE_THREAD_COUNT 0x00000035U
-#define MSR_LASTBRANCH_0_FROM_IP 0x00000040U
-#define MSR_LASTBRANCH_1_FROM_IP 0x00000041U
-#define MSR_LASTBRANCH_2_FROM_IP 0x00000042U
-#define MSR_LASTBRANCH_3_FROM_IP 0x00000043U
-#define MSR_LASTBRANCH_4_FROM_IP 0x00000044U
-#define MSR_LASTBRANCH_5_FROM_IP 0x00000045U
-#define MSR_LASTBRANCH_6_FROM_IP 0x00000046U
-#define MSR_LASTBRANCH_7_FROM_IP 0x00000047U
#define MSR_PPIN_CTL 0x0000004EU
#define MSR_PPIN 0x0000004FU
#define MSR_THREAD_ID_INFO 0x00000053U
@@ -403,7 +395,7 @@
#define MSR_TURBO_GROUP_CORECNT 0x000001AEU
#define MSR_TURBO_RATIO_LIMIT2 0x000001AFU
#define MSR_LBR_SELECT 0x000001C8U
-#define MSR_LASTBRANCH_TOS 0x000001DAU
+#define MSR_LASTBRANCH_TOS 0x000001C9U
#define MSR_LASTBRANCH_0 0x000001DBU
#define MSR_LASTBRANCH_1 0x000001DCU
#define MSR_LASTBRANCH_2 0x000001DDU
@@ -494,9 +486,70 @@
#define MSR_ATOM_PKG_POWER_INFO 0x0000066EU
#define MSR_RING_PERF_LIMIT_REASONS 0x00000681U
#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690U
+#define MSR_LASTBRANCH_0_FROM_IP 0x00000680U
+#define MSR_LASTBRANCH_1_FROM_IP 0x00000681U
+#define MSR_LASTBRANCH_2_FROM_IP 0x00000682U
+#define MSR_LASTBRANCH_3_FROM_IP 0x00000683U
+#define MSR_LASTBRANCH_4_FROM_IP 0x00000684U
+#define MSR_LASTBRANCH_5_FROM_IP 0x00000685U
+#define MSR_LASTBRANCH_6_FROM_IP 0x00000686U
+#define MSR_LASTBRANCH_7_FROM_IP 0x00000687U
+#define MSR_LASTBRANCH_8_FROM_IP 0x00000688U
+#define MSR_LASTBRANCH_9_FROM_IP 0x00000689U
+#define MSR_LASTBRANCH_10_FROM_IP 0x0000068AU
+#define MSR_LASTBRANCH_11_FROM_IP 0x0000068BU
+#define MSR_LASTBRANCH_12_FROM_IP 0x0000068CU
+#define MSR_LASTBRANCH_13_FROM_IP 0x0000068DU
+#define MSR_LASTBRANCH_14_FROM_IP 0x0000068EU
+#define MSR_LASTBRANCH_15_FROM_IP 0x0000068FU
+#define MSR_LASTBRANCH_16_FROM_IP 0x00000690U
+#define MSR_LASTBRANCH_17_FROM_IP 0x00000691U
+#define MSR_LASTBRANCH_18_FROM_IP 0x00000692U
+#define MSR_LASTBRANCH_19_FROM_IP 0x00000693U
+#define MSR_LASTBRANCH_20_FROM_IP 0x00000694U
+#define MSR_LASTBRANCH_21_FROM_IP 0x00000695U
+#define MSR_LASTBRANCH_22_FROM_IP 0x00000696U
+#define MSR_LASTBRANCH_23_FROM_IP 0x00000697U
+#define MSR_LASTBRANCH_24_FROM_IP 0x00000698U
+#define MSR_LASTBRANCH_25_FROM_IP 0x00000699U
+#define MSR_LASTBRANCH_26_FROM_IP 0x0000069AU
+#define MSR_LASTBRANCH_27_FROM_IP 0x0000069BU
+#define MSR_LASTBRANCH_28_FROM_IP 0x0000069CU
+#define MSR_LASTBRANCH_29_FROM_IP 0x0000069DU
+#define MSR_LASTBRANCH_30_FROM_IP 0x0000069EU
#define MSR_LASTBRANCH_31_FROM_IP 0x0000069FU
#define MSR_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0U
#define MSR_LASTBRANCH_0_TO_IP 0x000006C0U
+#define MSR_LASTBRANCH_1_TO_IP 0x000006C1U
+#define MSR_LASTBRANCH_2_TO_IP 0x000006C2U
+#define MSR_LASTBRANCH_3_TO_IP 0x000006C3U
+#define MSR_LASTBRANCH_4_TO_IP 0x000006C4U
+#define MSR_LASTBRANCH_5_TO_IP 0x000006C5U
+#define MSR_LASTBRANCH_6_TO_IP 0x000006C6U
+#define MSR_LASTBRANCH_7_TO_IP 0x000006C7U
+#define MSR_LASTBRANCH_8_TO_IP 0x000006C8U
+#define MSR_LASTBRANCH_9_TO_IP 0x000006C9U
+#define MSR_LASTBRANCH_10_TO_IP 0x000006CAU
+#define MSR_LASTBRANCH_11_TO_IP 0x000006CBU
+#define MSR_LASTBRANCH_12_TO_IP 0x000006CCU
+#define MSR_LASTBRANCH_13_TO_IP 0x000006CDU
+#define MSR_LASTBRANCH_14_TO_IP 0x000006CEU
+#define MSR_LASTBRANCH_15_TO_IP 0x000006CFU
+#define MSR_LASTBRANCH_16_TO_IP 0x000006D0U
+#define MSR_LASTBRANCH_17_TO_IP 0x000006D1U
+#define MSR_LASTBRANCH_18_TO_IP 0x000006D2U
+#define MSR_LASTBRANCH_19_TO_IP 0x000006D3U
+#define MSR_LASTBRANCH_20_TO_IP 0x000006D4U
+#define MSR_LASTBRANCH_21_TO_IP 0x000006D5U
+#define MSR_LASTBRANCH_22_TO_IP 0x000006D6U
+#define MSR_LASTBRANCH_23_TO_IP 0x000006D7U
+#define MSR_LASTBRANCH_24_TO_IP 0x000006D8U
+#define MSR_LASTBRANCH_25_TO_IP 0x000006D9U
+#define MSR_LASTBRANCH_26_TO_IP 0x000006DAU
+#define MSR_LASTBRANCH_27_TO_IP 0x000006DBU
+#define MSR_LASTBRANCH_28_TO_IP 0x000006DCU
+#define MSR_LASTBRANCH_29_TO_IP 0x000006DDU
+#define MSR_LASTBRANCH_30_TO_IP 0x000006DEU
#define MSR_LASTBRANCH_31_TO_IP 0x000006DFU
#define MSR_IA32_L2_QOS_MASK_0 0x00000D10U
#define MSR_IA32_L2_QOS_MASK_1 0x00000D11U
@@ -513,6 +566,8 @@
#define MSR_EMON_L3_CTR_CTL5 0x000107D1U
#define MSR_EMON_L3_CTR_CTL6 0x000107D2U
#define MSR_EMON_L3_CTR_CTL7 0x000107D3U
+#define MSR_LER_FROM_LIP 0x000001DDU
+#define MSR_LER_TO_LIP 0x000001DEU

#ifdef PROFILING_ON
/* Core (and Goldmont) specific MSRs */
--
2.17.1


Xu, Anthony
 

What do you mean " Some debug MSRs are unsupported in hypervisor"

Can we pass-through debug MSR to guest?

Anthony

-----Original Message-----
From: acrn-dev@lists.projectacrn.org [mailto:acrn-dev@lists.projectacrn.org] On Behalf Of Jiang
Sent: Thursday, August 15, 2019 1:04 AM
To: acrn-dev@lists.projectacrn.org
Cc: Jiang, MaoX <maox.jiang@intel.com>
Subject: [acrn-dev] [PATCH 1/1] hv: fix read/write some debug MSRs without #GP received

Some debug MSRs are unsupported in hypervisor, when read/write these MSRs, hypervisor do not intercept it. This patch
add connected MSRs into unsupported_msrs array, hypervisor will intercept debug MSRs and inject #GP to guest.

Tracked-On: #3569
Signed-off-by: Jiang Mao<maox.jiang@intel.com>
---
hypervisor/arch/x86/guest/vmsr.c | 73 ++++++++++++++++++++++++++++++-
hypervisor/include/arch/x86/msr.h | 73 +++++++++++++++++++++++++++----
2 files changed, 136 insertions(+), 10 deletions(-)

diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index 26acd703..8202e648 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -78,7 +78,7 @@ static const uint32_t mtrr_msrs[NUM_MTRR_MSRS] = {
};

/* Following MSRs are intercepted, but it throws GPs for any guest accesses */
-#define NUM_UNSUPPORTED_MSRS 99U
+#define NUM_UNSUPPORTED_MSRS 168U
static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
/* Variable MTRRs are not supported */
MSR_IA32_MTRR_PHYSBASE_0,
@@ -201,6 +201,77 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {

/* Performance Monitoring: CPUID.01H.ECX[15] X86_FEATURE_PDCM */
MSR_IA32_PERF_CAPABILITIES,
+ MSR_IA32_DEBUGCTL,
+
+ /* Last Branch Record (LBR) Stack disabled */
+ MSR_LBR_SELECT,
+ MSR_LER_TO_LIP,
+ MSR_LER_FROM_LIP,
+ MSR_LASTBRANCH_TOS,
+ MSR_LASTBRANCH_0_FROM_IP,
+ MSR_LASTBRANCH_1_FROM_IP,
+ MSR_LASTBRANCH_2_FROM_IP,
+ MSR_LASTBRANCH_3_FROM_IP,
+ MSR_LASTBRANCH_4_FROM_IP,
+ MSR_LASTBRANCH_5_FROM_IP,
+ MSR_LASTBRANCH_6_FROM_IP,
+ MSR_LASTBRANCH_7_FROM_IP,
+ MSR_LASTBRANCH_8_FROM_IP,
+ MSR_LASTBRANCH_9_FROM_IP,
+ MSR_LASTBRANCH_10_FROM_IP,
+ MSR_LASTBRANCH_11_FROM_IP,
+ MSR_LASTBRANCH_12_FROM_IP,
+ MSR_LASTBRANCH_13_FROM_IP,
+ MSR_LASTBRANCH_14_FROM_IP,
+ MSR_LASTBRANCH_15_FROM_IP,
+ MSR_LASTBRANCH_16_FROM_IP,
+ MSR_LASTBRANCH_17_FROM_IP,
+ MSR_LASTBRANCH_18_FROM_IP,
+ MSR_LASTBRANCH_19_FROM_IP,
+ MSR_LASTBRANCH_20_FROM_IP,
+ MSR_LASTBRANCH_21_FROM_IP,
+ MSR_LASTBRANCH_22_FROM_IP,
+ MSR_LASTBRANCH_23_FROM_IP,
+ MSR_LASTBRANCH_24_FROM_IP,
+ MSR_LASTBRANCH_25_FROM_IP,
+ MSR_LASTBRANCH_26_FROM_IP,
+ MSR_LASTBRANCH_27_FROM_IP,
+ MSR_LASTBRANCH_28_FROM_IP,
+ MSR_LASTBRANCH_29_FROM_IP,
+ MSR_LASTBRANCH_30_FROM_IP,
+ MSR_LASTBRANCH_31_FROM_IP,
+ MSR_LASTBRANCH_0_TO_IP,
+ MSR_LASTBRANCH_1_TO_IP,
+ MSR_LASTBRANCH_2_TO_IP,
+ MSR_LASTBRANCH_3_TO_IP,
+ MSR_LASTBRANCH_4_TO_IP,
+ MSR_LASTBRANCH_5_TO_IP,
+ MSR_LASTBRANCH_6_TO_IP,
+ MSR_LASTBRANCH_7_TO_IP,
+ MSR_LASTBRANCH_8_TO_IP,
+ MSR_LASTBRANCH_9_TO_IP,
+ MSR_LASTBRANCH_10_TO_IP,
+ MSR_LASTBRANCH_11_TO_IP,
+ MSR_LASTBRANCH_12_TO_IP,
+ MSR_LASTBRANCH_13_TO_IP,
+ MSR_LASTBRANCH_14_TO_IP,
+ MSR_LASTBRANCH_15_TO_IP,
+ MSR_LASTBRANCH_16_TO_IP,
+ MSR_LASTBRANCH_17_TO_IP,
+ MSR_LASTBRANCH_18_TO_IP,
+ MSR_LASTBRANCH_19_TO_IP,
+ MSR_LASTBRANCH_20_TO_IP,
+ MSR_LASTBRANCH_21_TO_IP,
+ MSR_LASTBRANCH_22_TO_IP,
+ MSR_LASTBRANCH_23_TO_IP,
+ MSR_LASTBRANCH_24_TO_IP,
+ MSR_LASTBRANCH_25_TO_IP,
+ MSR_LASTBRANCH_26_TO_IP,
+ MSR_LASTBRANCH_27_TO_IP,
+ MSR_LASTBRANCH_28_TO_IP,
+ MSR_LASTBRANCH_29_TO_IP,
+ MSR_LASTBRANCH_30_TO_IP,
+ MSR_LASTBRANCH_31_TO_IP,

/* Debug Store disabled: CPUID.01H.EDX[21] X86_FEATURE_DTES */
MSR_IA32_DS_AREA,
diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h
index 1eea6a1a..660fe500 100644
--- a/hypervisor/include/arch/x86/msr.h
+++ b/hypervisor/include/arch/x86/msr.h
@@ -361,14 +361,6 @@
#define MSR_EBC_FREQUENCY_ID 0x0000002CU
#define MSR_SMI_COUNT 0x00000034U
#define MSR_CORE_THREAD_COUNT 0x00000035U
-#define MSR_LASTBRANCH_0_FROM_IP 0x00000040U
-#define MSR_LASTBRANCH_1_FROM_IP 0x00000041U
-#define MSR_LASTBRANCH_2_FROM_IP 0x00000042U
-#define MSR_LASTBRANCH_3_FROM_IP 0x00000043U
-#define MSR_LASTBRANCH_4_FROM_IP 0x00000044U
-#define MSR_LASTBRANCH_5_FROM_IP 0x00000045U
-#define MSR_LASTBRANCH_6_FROM_IP 0x00000046U
-#define MSR_LASTBRANCH_7_FROM_IP 0x00000047U
#define MSR_PPIN_CTL 0x0000004EU
#define MSR_PPIN 0x0000004FU
#define MSR_THREAD_ID_INFO 0x00000053U
@@ -403,7 +395,7 @@
#define MSR_TURBO_GROUP_CORECNT 0x000001AEU
#define MSR_TURBO_RATIO_LIMIT2 0x000001AFU
#define MSR_LBR_SELECT 0x000001C8U
-#define MSR_LASTBRANCH_TOS 0x000001DAU
+#define MSR_LASTBRANCH_TOS 0x000001C9U
#define MSR_LASTBRANCH_0 0x000001DBU
#define MSR_LASTBRANCH_1 0x000001DCU
#define MSR_LASTBRANCH_2 0x000001DDU
@@ -494,9 +486,70 @@
#define MSR_ATOM_PKG_POWER_INFO 0x0000066EU
#define MSR_RING_PERF_LIMIT_REASONS 0x00000681U
#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690U
+#define MSR_LASTBRANCH_0_FROM_IP 0x00000680U
+#define MSR_LASTBRANCH_1_FROM_IP 0x00000681U
+#define MSR_LASTBRANCH_2_FROM_IP 0x00000682U
+#define MSR_LASTBRANCH_3_FROM_IP 0x00000683U
+#define MSR_LASTBRANCH_4_FROM_IP 0x00000684U
+#define MSR_LASTBRANCH_5_FROM_IP 0x00000685U
+#define MSR_LASTBRANCH_6_FROM_IP 0x00000686U
+#define MSR_LASTBRANCH_7_FROM_IP 0x00000687U
+#define MSR_LASTBRANCH_8_FROM_IP 0x00000688U
+#define MSR_LASTBRANCH_9_FROM_IP 0x00000689U
+#define MSR_LASTBRANCH_10_FROM_IP 0x0000068AU
+#define MSR_LASTBRANCH_11_FROM_IP 0x0000068BU
+#define MSR_LASTBRANCH_12_FROM_IP 0x0000068CU
+#define MSR_LASTBRANCH_13_FROM_IP 0x0000068DU
+#define MSR_LASTBRANCH_14_FROM_IP 0x0000068EU
+#define MSR_LASTBRANCH_15_FROM_IP 0x0000068FU
+#define MSR_LASTBRANCH_16_FROM_IP 0x00000690U
+#define MSR_LASTBRANCH_17_FROM_IP 0x00000691U
+#define MSR_LASTBRANCH_18_FROM_IP 0x00000692U
+#define MSR_LASTBRANCH_19_FROM_IP 0x00000693U
+#define MSR_LASTBRANCH_20_FROM_IP 0x00000694U
+#define MSR_LASTBRANCH_21_FROM_IP 0x00000695U
+#define MSR_LASTBRANCH_22_FROM_IP 0x00000696U
+#define MSR_LASTBRANCH_23_FROM_IP 0x00000697U
+#define MSR_LASTBRANCH_24_FROM_IP 0x00000698U
+#define MSR_LASTBRANCH_25_FROM_IP 0x00000699U
+#define MSR_LASTBRANCH_26_FROM_IP 0x0000069AU
+#define MSR_LASTBRANCH_27_FROM_IP 0x0000069BU
+#define MSR_LASTBRANCH_28_FROM_IP 0x0000069CU
+#define MSR_LASTBRANCH_29_FROM_IP 0x0000069DU
+#define MSR_LASTBRANCH_30_FROM_IP 0x0000069EU
#define MSR_LASTBRANCH_31_FROM_IP 0x0000069FU
#define MSR_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0U
#define MSR_LASTBRANCH_0_TO_IP 0x000006C0U
+#define MSR_LASTBRANCH_1_TO_IP 0x000006C1U
+#define MSR_LASTBRANCH_2_TO_IP 0x000006C2U
+#define MSR_LASTBRANCH_3_TO_IP 0x000006C3U
+#define MSR_LASTBRANCH_4_TO_IP 0x000006C4U
+#define MSR_LASTBRANCH_5_TO_IP 0x000006C5U
+#define MSR_LASTBRANCH_6_TO_IP 0x000006C6U
+#define MSR_LASTBRANCH_7_TO_IP 0x000006C7U
+#define MSR_LASTBRANCH_8_TO_IP 0x000006C8U
+#define MSR_LASTBRANCH_9_TO_IP 0x000006C9U
+#define MSR_LASTBRANCH_10_TO_IP 0x000006CAU
+#define MSR_LASTBRANCH_11_TO_IP 0x000006CBU
+#define MSR_LASTBRANCH_12_TO_IP 0x000006CCU
+#define MSR_LASTBRANCH_13_TO_IP 0x000006CDU
+#define MSR_LASTBRANCH_14_TO_IP 0x000006CEU
+#define MSR_LASTBRANCH_15_TO_IP 0x000006CFU
+#define MSR_LASTBRANCH_16_TO_IP 0x000006D0U
+#define MSR_LASTBRANCH_17_TO_IP 0x000006D1U
+#define MSR_LASTBRANCH_18_TO_IP 0x000006D2U
+#define MSR_LASTBRANCH_19_TO_IP 0x000006D3U
+#define MSR_LASTBRANCH_20_TO_IP 0x000006D4U
+#define MSR_LASTBRANCH_21_TO_IP 0x000006D5U
+#define MSR_LASTBRANCH_22_TO_IP 0x000006D6U
+#define MSR_LASTBRANCH_23_TO_IP 0x000006D7U
+#define MSR_LASTBRANCH_24_TO_IP 0x000006D8U
+#define MSR_LASTBRANCH_25_TO_IP 0x000006D9U
+#define MSR_LASTBRANCH_26_TO_IP 0x000006DAU
+#define MSR_LASTBRANCH_27_TO_IP 0x000006DBU
+#define MSR_LASTBRANCH_28_TO_IP 0x000006DCU
+#define MSR_LASTBRANCH_29_TO_IP 0x000006DDU
+#define MSR_LASTBRANCH_30_TO_IP 0x000006DEU
#define MSR_LASTBRANCH_31_TO_IP 0x000006DFU
#define MSR_IA32_L2_QOS_MASK_0 0x00000D10U
#define MSR_IA32_L2_QOS_MASK_1 0x00000D11U
@@ -513,6 +566,8 @@
#define MSR_EMON_L3_CTR_CTL5 0x000107D1U
#define MSR_EMON_L3_CTR_CTL6 0x000107D2U
#define MSR_EMON_L3_CTR_CTL7 0x000107D3U
+#define MSR_LER_FROM_LIP 0x000001DDU
+#define MSR_LER_TO_LIP 0x000001DEU

#ifdef PROFILING_ON
/* Core (and Goldmont) specific MSRs */
--
2.17.1