HI, Eddie

#ac

When the destination of an atomic memory operation located in 2 cache lines, it is called a Splitlock Access. LOCK# bus signal is asserted for splitlock access which may lead to long latency. #AC for

#ac

This patch is actually only for adding core capability enumaration, please give out correct commit message.

#ac

If CPU support rise #AC for Splitlock Access, then enable this feature at each CPU. Tracked-On: #4496 Signed-off-by: Tao Yuhong <yuhong.tao@...> --- hypervisor/arch/x86/cpu.c | 15 ++++++++++++++

#ac

When the destination of an atomic memory operation located in 2 cache lines, it is called a Splitlock Access. LOCK# bus signal is asserted for splitlock access which may lead to long latency. #AC for

#ac

This is completely wrong assumption. HV should never trigger #AC, This is design philosophy.

#ac

Hi, Eddie

#ac

Hi, Eddie

#ac

Hi, Fei

#ac

Once Splitlock Access happens in HV, alignment check exception handler will disable splitlock detection, that allows HV go on running. We can re-enabled it at every VM-Exit, to make sure #AC for split

#ac

When the destination of an atomic memory operation located in 2 cache lines, it is called a Splitlock Access. LOCK# bus signal is asserted for splitlock access which can reduce performance. #AC for Sp

#ac