Acked-by: Yu Wang <yu1.wang@...>

This patch enable the support for SOS S3 from the perspective of USB xHCI. Signed-off-by: Xiaoguang Wu <xiaoguang.wu@...> Reviewed-by: Liang Yang <liang3.yang@...> ---

The xHCI emulation greatly depends on the user space library libusb which is based on the usbfs module in Linux kernel. The libusb will bind usbfs to physical USB device which makes hardware control

Replace 'native_assign_ports' with 'port_map_tbl' to be more accurate for the role of this variable plays. Signed-off-by: Xiaoguang Wu <xiaoguang.wu@...> Reviewed-by: Liang Yang

Currently the maximum number of bus and port for xHCI are both set to 255, it is theoretically possible but in fact not neccessary. This patch changes those two values to be more proper: 4 buses and

Current design cannot get physical USB device information without the creation of pci_xhci_dev_emu. This brings some difficulties in certain situations, hence struct usb_native_devinfo is

The variable native_assign_ports in struct pci_xhci_vdev is used to record wether certain root hub port in SOS is assigned to UOS. The logic uses zero to express 'not assigned' and nonzero to

PORTSC (Port Status and Control Register) register play a very important role in USB sub-system. This patch is used to refine related manipulation functions. Signed-off-by: Xiaoguang Wu

Current DM design use two variables to do the indexing of xHCI Event Ring: er_enq_idx and er_events_cnt. They are members of the struct pci_xhci_rtsregs. In UOS, during the process of xHCI resuming,

This patchset enable the USB xHCI S3 feature. Xiaoguang Wu (8): DM USB: xHCI: fix an xHCI issue to enable UOS s3 feature DM USB: xHCI: refine xHCI PORTSC Register related functions DM USB:

For the instructions other than MOVS and STO, the gva comes from instruction decoding. Apply the gva check for this type of gva and inject exception to guest accordingly during instruction decoding

MOVS and STO instruction get the operand line address from DI and SI. This patch adds line address check after instruction decoding is done. Inject exception accordingly if check fails. We add check

Drop the get_gla function and add - get_gva_di_si_nocheck get gva from ES:DI and DS(other segment):SI without check faulure case - get_gva_di_si_check get gva from ES:DI and DS(other

We will do check only during instruction decode phase. vie_calculate_gla will be called both in instruction emulation phase, we move the check out of vie_calculate_gla. Signed-off-by: Yin Fengwei

According to SDM vol3 25.1.1 With VMX enabled, following exception will be handled by guest without trigger VM exit: - faults based on privilege level - general protection due to relevent segment

According to SDM Vol2 - Instruction Set Reference: Some instructions can't work with prefix lock or can't work in some situations (destination is not a memory operand). We add the lock prefix check

Fix two use without initialization build error in instr_emul.c Signed-off-by: Yin Fengwei <fengwei.yin@...> --- hypervisor/arch/x86/guest/instr_emul.c | 4 ++-- 1 file changed, 2

If rm show there is no SIB following rm field, we should get base_register info from rm. --- hypervisor/arch/x86/guest/instr_emul.c | 42 +++++++++++++++++++++++++- 1 file changed, 41 insertions(+),

According to SDM, we should check whether the gva access from guest is valid. If it's not, correct exception should be injected. We only need to emulate the instructions which access the memory and

From: Mingqiang Chi <mingqiang.chi@...> -- Change these APIs to void type, add pre-conditions, and move parameter-check to upper-layer functions. handle_vpic_irqline vpic_set_irqstate