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[PATCH v2] add an IRQ chip to gpio-virtio GPIO chip.
use two virtqueues for irq function, one for handling irq chip
operations and one for handling interrupt. The irqchip supports
level and edge trigger modes.
v2: replace spin_lock_irqsave with
use two virtqueues for irq function, one for handling irq chip
operations and one for handling interrupt. The irqchip supports
level and edge trigger modes.
v2: replace spin_lock_irqsave with
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By
Liu Yuan
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#19314
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Re: [PATCH] hv: vlapic: add combined constraint to enable APICv
By
Xu, Anthony
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#19313
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Re: [PATCH 1/2] HV: PAE: Add stac()/clac() in local_gva2gpa_pae
By
Kaige Fu
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#19312
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[PATCH] HV: Modularize bsp folder
V1:
Remove usage of hypervisor.h from inside
BSP folder.
Replace with only the required header files.
V2:
Added vm.h to ptdev.h to fix 4 potential
MISRA-C violations.
Tracked-On:
V1:
Remove usage of hypervisor.h from inside
BSP folder.
Replace with only the required header files.
V2:
Added vm.h to ptdev.h to fix 4 potential
MISRA-C violations.
Tracked-On:
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By
Arindam Roy <arindam.roy@...>
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#19311
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[PATCH] HV: Modularize bsp folder
Remove usage of hypervisor.h from inside
BSP folder.
Replace with only the required header files.
Tracked-On: #2893
Signed-off-by: Arindam Roy <arindam.roy@...>
---
Remove usage of hypervisor.h from inside
BSP folder.
Replace with only the required header files.
Tracked-On: #2893
Signed-off-by: Arindam Roy <arindam.roy@...>
---
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By
Arindam Roy <arindam.roy@...>
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#19310
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Re: [PATCH] hv: Remove multiple definitions for dmar translation structures
It is coding style change.
Binbin/Jason,
Comments?
Anthony
It is coding style change.
Binbin/Jason,
Comments?
Anthony
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By
Xu, Anthony
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#19309
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[PATCH] hv: Remove multiple definitions for dmar translation structures
Except for few translation structures in x86 IOMMU, all translation
structures are 128-bit. All the translation structures used by ACRN
are 128 bit. So removed multiple definitions and defined a
Except for few translation structures in x86 IOMMU, all translation
structures are 128-bit. All the translation structures used by ACRN
are 128 bit. So removed multiple definitions and defined a
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By
Grandhi, Sainath
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#19308
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Re: [PATCH 1/2] HV: PAE: Add stac()/clac() in local_gva2gpa_pae
Just curious, this path was not invoked for other guests?
Just curious, this path was not invoked for other guests?
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By
Grandhi, Sainath
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#19307
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Re: COM_IRQ type is hex in Kconfig
Thanks!
By
Geoffroy Van Cutsem
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#19306
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Re: COM_IRQ type is hex in Kconfig
Let me check that, and will keep it consist.
Let me check that, and will keep it consist.
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By
Minggui Cao
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#19305
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[PATCH 2/2] DM: Don't check thre_int_pending before firing interrupt
There are uart drivers which send data to hardware in ISR, like zephyr.
Zephyr stores data in tx_ringbuf and then write the IER of UART to trigger
tx interrupt. Finally, it write the data stored in
There are uart drivers which send data to hardware in ISR, like zephyr.
Zephyr stores data in tx_ringbuf and then write the IER of UART to trigger
tx interrupt. Finally, it write the data stored in
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By
Kaige Fu
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#19304
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[PATCH 1/2] HV: PAE: Add stac()/clac() in local_gva2gpa_pae
Accessing memory of guest will cause page fault when SMAP is enabled.
This patch stac()/clac() correspondingly to get rid of this situation.
Signed-off-by: Kaige Fu <kaige.fu@...>
---
Accessing memory of guest will cause page fault when SMAP is enabled.
This patch stac()/clac() correspondingly to get rid of this situation.
Signed-off-by: Kaige Fu <kaige.fu@...>
---
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By
Kaige Fu
·
#19303
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[PATCH 0/2] First patchset to enable zephyr as guest
Here is first patchset to enable zephyr as guest and contains two minor fix.
Kaige Fu (2):
HV: PAE: Add stac()/clac() in local_gva2gpa_pae
DM: Don't check thre_int_pending before firing
Here is first patchset to enable zephyr as guest and contains two minor fix.
Kaige Fu (2):
HV: PAE: Add stac()/clac() in local_gva2gpa_pae
DM: Don't check thre_int_pending before firing
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By
Kaige Fu
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#19302
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[PATCH v2 6/6] DM: virtio-gpio: export GPIO ACPI device
Add dsdt for virtio-gpio device.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
devicemodel/hw/pci/virtio/virtio_gpio.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git
Add dsdt for virtio-gpio device.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
devicemodel/hw/pci/virtio/virtio_gpio.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git
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By
Liu Yuan
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#19301
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[PATCH v2 5/6] DM: virtio-gpio: add IRQ statistics
print each IRQ descriptor interrupts number and all of IRQ descriptors
interrupts when UOS requests or releases a GPIO IRQ.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
print each IRQ descriptor interrupts number and all of IRQ descriptors
interrupts when UOS requests or releases a GPIO IRQ.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
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By
Liu Yuan
·
#19300
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[PATCH v2 4/6] DM: virtio-gpio: support reading value from IRQ descriptor
Support reading GPIO value when the GPIO switches to IRQ mode.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
devicemodel/hw/pci/virtio/virtio_gpio.c | 19 ++++++++++++++-----
1 file changed, 14
Support reading GPIO value when the GPIO switches to IRQ mode.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
devicemodel/hw/pci/virtio/virtio_gpio.c | 19 ++++++++++++++-----
1 file changed, 14
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By
Liu Yuan
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#19299
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[PATCH v2 3/6] DM: virtio-gpio: emulate GPIO IRQ controller
GPIO IRQ controller emulation is used to handle level trigger and
edge trigger interrupts. Use GPIO IRQ virtqueue to handle IRQ chip
operations and GPIO event virtqueue to indicate IRQ source to
GPIO IRQ controller emulation is used to handle level trigger and
edge trigger interrupts. Use GPIO IRQ virtqueue to handle IRQ chip
operations and GPIO event virtqueue to indicate IRQ source to
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By
Liu Yuan
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#19298
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[PATCH v2 2/6] DM: virtio-gpio: GPIO IRQ initialization.
add the GPIO IRQ definitions, and implement the GPIO IRQ
initialization and deinitialization.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
devicemodel/hw/pci/virtio/virtio_gpio.c | 77
add the GPIO IRQ definitions, and implement the GPIO IRQ
initialization and deinitialization.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
devicemodel/hw/pci/virtio/virtio_gpio.c | 77
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By
Liu Yuan
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#19297
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[PATCH v2 1/6] DM: virtio-gpio: setup two virqueues for gpio irq
There are two virtqueues for irq, one for handling the operations of
front-end irq controller and the other for triggering the interrupt.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
There are two virtqueues for irq, one for handling the operations of
front-end irq controller and the other for triggering the interrupt.
Signed-off-by: Yuan Liu <yuan1.liu@...>
---
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By
Liu Yuan
·
#19296
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[PATCH v2 0/6] DM: virtio-gpio: implement GPIO IRQ
virtio GPIO IRQ emaulates a GPIO IRQ controller to support
level trigger and edge trigger interrupts, it uses two virtqueues
one is for IRQ chip operations and another is to notify IRQ sources.
Yuan
virtio GPIO IRQ emaulates a GPIO IRQ controller to support
level trigger and edge trigger interrupts, it uses two virtqueues
one is for IRQ chip operations and another is to notify IRQ sources.
Yuan
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By
Liu Yuan
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#19295
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