Date   

Re: [V3] ACRN: DM: Fix the MSI mask and unmask bugs.

Yu Wang
 

Acked-by: Wang, Yu1 <yu1.wang@...>

On Fri, Jun 10, 2022 at 08:55:45AM +0800, Liu Long wrote:
The patch fix many bugs about the pci msi capabilities.
1. Fix the clear msi mask bit issues.
2. Initialize the offset of pci capabilities this variable will used as
the output of pci_emul_find_capability function.
3. Replace 16-read with 32-read because both mask and pending are 32bit.
4. Add mask and pending element in msicap struct and intialize the struct
value to zero, because we need r/w mask and pending value.

Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..9f6256bc6 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen)
int
pci_emul_find_capability(struct pci_vdev *dev, uint8_t capid, int *p_capoff)
{
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS);
@@ -1069,7 +1069,7 @@ static int
pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
{
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n", __func__);
@@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + PCIR_MSI_CTRL);
if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true);
}

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
int
pci_emul_add_msicap(struct pci_vdev *dev, int msgnum)
{
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h b/devicemodel/include/pci_core.h
index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion failed");

struct msixcap {
uint8_t capid;
--
2.25.1


[V3] ACRN: DM: Fix the MSI mask and unmask bugs.

Long Liu
 

The patch fix many bugs about the pci msi capabilities.
1. Fix the clear msi mask bit issues.
2. Initialize the offset of pci capabilities this variable will used as
the output of pci_emul_find_capability function.
3. Replace 16-read with 32-read because both mask and pending are 32bit.
4. Add mask and pending element in msicap struct and intialize the struct
value to zero, because we need r/w mask and pending value.

Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..9f6256bc6 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen)
int
pci_emul_find_capability(struct pci_vdev *dev, uint8_t capid, int *p_capoff)
{
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS);
@@ -1069,7 +1069,7 @@ static int
pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
{
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n", __func__);
@@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + PCIR_MSI_CTRL);
if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true);
}

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
int
pci_emul_add_msicap(struct pci_vdev *dev, int msgnum)
{
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h b/devicemodel/include/pci_core.h
index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion failed");

struct msixcap {
uint8_t capid;
--
2.25.1


[V2] ACRN: DM: Fix the MSI mask and unmask bugs.

Long Liu
 

The patch fix many bugs about the pci msi capabilities.
1. Fix the clear msi mask bit issues.
2. Initialize the offset of pci capabilities this variable will used as
the output of pci_emul_find_capability function.
3. Replace 16-read with 32-read because both mask and pending are 32bit.
4. Add mask and pending element in msicap struct and intialize the struct
value to zero, because we need r/w mask and pending value.

Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..e44045b12 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen)
int
pci_emul_find_capability(struct pci_vdev *dev, uint8_t capid, int *p_capoff)
{
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS);
@@ -1069,7 +1069,7 @@ static int
pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
{
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n", __func__);
@@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + 2);
if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true);
}

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
int
pci_emul_add_msicap(struct pci_vdev *dev, int msgnum)
{
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h b/devicemodel/include/pci_core.h
index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion failed");

struct msixcap {
uint8_t capid;
--
2.25.1


Re: [PATCH] ACRN: DM: Fix the MSI mask and unmask bugs.

Yu Wang
 

On Thu, Jun 09, 2022 at 09:03:35AM +0000, Long Liu wrote:
-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On Behalf Of Yu Wang
Sent: Wednesday, June 8, 2022 7:50 PM
To: Liu Long <long.liu@...>
Cc: acrn-dev@...; Li, Fei1 <fei1.li@...>
Subject: Re: [acrn-dev] [PATCH] ACRN: DM: Fix the MSI mask and unmask bugs.

On Wed, Jun 08, 2022 at 04:35:07PM +0800, Liu Long wrote:
The patch fix the msi clear pending bit issue, add new struct element
in the msicap struct, we will use this element by address pointer.
Please explain the detailed fixes. This patch has several fix, please
list them one by one.


Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..e44045b12 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev,
u_char *capdata, int caplen) int pci_emul_find_capability(struct
pci_vdev *dev, uint8_t capid, int *p_capoff) {
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS); @@ -1069,7 +1069,7 @@
static int pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t
*val, bool is_write) {
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n",
__func__); @@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + 2);
offset + PCIR_MSI_CTRL

if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true); }

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int
msgnum, int nextptr) int pci_emul_add_msicap(struct pci_vdev *dev,
int msgnum) {
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h
b/devicemodel/include/pci_core.h index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
If you add such fields into the msicap, then we should use them to check mask and pending? Otherwise, what're their meaning?

[Long:] We will use these fields by address pointer, just like the base + offset.
I see.


} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion
failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion
+failed");

struct msixcap {
uint8_t capid;
--
2.25.1









Re: [PATCH] ACRN: DM: Fix the MSI mask and unmask bugs.

Long Liu
 

-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On Behalf Of Yu Wang
Sent: Wednesday, June 8, 2022 7:50 PM
To: Liu Long <long.liu@...>
Cc: acrn-dev@...; Li, Fei1 <fei1.li@...>
Subject: Re: [acrn-dev] [PATCH] ACRN: DM: Fix the MSI mask and unmask bugs.

On Wed, Jun 08, 2022 at 04:35:07PM +0800, Liu Long wrote:
The patch fix the msi clear pending bit issue, add new struct element
in the msicap struct, we will use this element by address pointer.

Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..e44045b12 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev,
u_char *capdata, int caplen) int pci_emul_find_capability(struct
pci_vdev *dev, uint8_t capid, int *p_capoff) {
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS); @@ -1069,7 +1069,7 @@
static int pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t
*val, bool is_write) {
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n",
__func__); @@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + 2);
offset + PCIR_MSI_CTRL

if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true); }

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int
msgnum, int nextptr) int pci_emul_add_msicap(struct pci_vdev *dev,
int msgnum) {
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h
b/devicemodel/include/pci_core.h index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
If you add such fields into the msicap, then we should use them to check mask and pending? Otherwise, what're their meaning?

[Long:] We will use these fields by address pointer, just like the base + offset.

} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion
failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion
+failed");

struct msixcap {
uint8_t capid;
--
2.25.1


Re: [PATCH] ACRN: DM: Fix the MSI mask and unmask bugs.

Yu Wang
 

On Wed, Jun 08, 2022 at 04:35:07PM +0800, Liu Long wrote:
The patch fix the msi clear pending bit issue, add new struct element
in the msicap struct, we will use this element by address pointer.

Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..e44045b12 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen)
int
pci_emul_find_capability(struct pci_vdev *dev, uint8_t capid, int *p_capoff)
{
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS);
@@ -1069,7 +1069,7 @@ static int
pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
{
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n", __func__);
@@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + 2);
offset + PCIR_MSI_CTRL

if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true);
}

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
int
pci_emul_add_msicap(struct pci_vdev *dev, int msgnum)
{
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h b/devicemodel/include/pci_core.h
index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
If you add such fields into the msicap, then we should use them to check
mask and pending? Otherwise, what're their meaning?

} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion failed");

struct msixcap {
uint8_t capid;
--
2.25.1


[PATCH] ACRN: DM: Fix the MSI mask and unmask bugs.

Long Liu
 

The patch fix the msi clear pending bit issue, add new struct element
in the msicap struct, we will use this element by address pointer.

Signed-off-by: Liu Long <long.liu@...>
---
devicemodel/hw/pci/core.c | 13 ++++++-------
devicemodel/include/pci_core.h | 5 ++++-
2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c
index 4f52a76a4..e44045b12 100644
--- a/devicemodel/hw/pci/core.c
+++ b/devicemodel/hw/pci/core.c
@@ -961,7 +961,7 @@ pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen)
int
pci_emul_find_capability(struct pci_vdev *dev, uint8_t capid, int *p_capoff)
{
- int coff;
+ int coff = 0;
uint16_t sts;

sts = pci_get_cfgdata16(dev, PCIR_STATUS);
@@ -1069,7 +1069,7 @@ static int
pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
{
uint16_t msgctrl;
- int rc, offset;
+ int rc, offset = 0;

if (msi_cap > PCIR_MSI_PENDING) {
pr_err("%s: Msi capability length is out of msi length!\n", __func__);
@@ -1079,7 +1079,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (rc)
return -1;

- msgctrl = pci_get_cfgdata16(dev, offset);
+ msgctrl = pci_get_cfgdata16(dev, offset + 2);
if (msgctrl & PCIM_MSICTRL_64BIT)
offset = offset + msi_cap;
else
@@ -1088,8 +1088,7 @@ pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write)
if (is_write)
pci_set_cfgdata32(dev, offset, *val);
else
- *val = pci_get_cfgdata16(dev, offset);
-
+ *val = pci_get_cfgdata32(dev, offset);
return 0;
}

@@ -1133,7 +1132,7 @@ pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set)
if (set)
val = (1 << index) | val;
else
- val = (~(1 << index)) | val;
+ val = (~(1 << index)) & val;
pci_access_msi(dev, PCIR_MSI_PENDING, &val, true);
}

@@ -1160,7 +1159,7 @@ pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
int
pci_emul_add_msicap(struct pci_vdev *dev, int msgnum)
{
- struct msicap msicap;
+ struct msicap msicap = {0};

return pci_populate_msicap(&msicap, msgnum, 0) ||
pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap));
diff --git a/devicemodel/include/pci_core.h b/devicemodel/include/pci_core.h
index 5aa562c3b..f24bb33bf 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -200,8 +200,11 @@ struct msicap {
uint32_t addrlo;
uint32_t addrhi;
uint16_t msgdata;
+ uint16_t reserve;
+ uint32_t maskbit;
+ uint32_t pendbit;
} __attribute__((packed));
-static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
+static_assert(sizeof(struct msicap) == 24, "compile-time assertion failed");

struct msixcap {
uint8_t capid;
--
2.25.1


Re: [PATCH] dm: add _CPC to guest ACPI when HWP is enabled

Yu Wang
 

On Mon, Jun 06, 2022 at 01:16:50PM +0000, Zhou, Wu wrote:
When running WaaG, we need to enable HWP to boost performance in
some scenarios. But when HWP is enabled in BIOS, windows does not
turn on HWP driver automatically just like Linux does. It requires
_CPC table in ACPI as well.

The _CPC table contains information about the HWP baseline registers.
Those regs are defined as architectural MSRs, so they should be the
same on different CPU models. Thus we can hard code the _CPC table.

When we turn off HWP in BIOS, windows's HWP driver will still be loaded
based on the _CPC table. This will cause the guest fail to boot.
So here we need read CPUID first, only add _CPC when HWP is enabled.

Tracked-On: #7695
Signed-off-by: Wu Zhou <wu.zhou@...>
---
devicemodel/hw/platform/acpi/acpi_pm.c | 57 ++++++++++++++++++++++++++
1 file changed, 57 insertions(+)

diff --git a/devicemodel/hw/platform/acpi/acpi_pm.c b/devicemodel/hw/platform/acpi/acpi_pm.c
index 5d953717ff..1e1a27b629 100644
--- a/devicemodel/hw/platform/acpi/acpi_pm.c
+++ b/devicemodel/hw/platform/acpi/acpi_pm.c
@@ -316,6 +316,51 @@ static int dsdt_write_pss(struct vmctx *ctx, int vcpu_id)
return 0;
}

+/* _CPC: Continuous Performance Control
+ * Hard code a V3 CPC table, describing HWP register interface.
+ */
+static void dsdt_write_cpc(void)
+{
+ dsdt_line("");
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (Package (0x17)");
+ dsdt_line(" {");
+ dsdt_line(" 0x17,");
+ dsdt_line(" 0x03,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x00000000000000CE, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E7, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E8, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x02, 0x01, 0x0000000000000777, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x01, 0x00, 0x0000000000000770, 0x04, )},");
+ dsdt_line(" One,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x0A, 0x20, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000774, 0x04, )},");
Please add comments to explain the detailed fields of each MSR like
like IA32_HWP_CAP(771H), MSR_PLATFORM_INFO, IA32_MPERF, etc.
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero");
+ dsdt_line(" })");
+ dsdt_line(" }");
+}
+
+static bool is_hwp_enabled(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+ do_cpuid(0x6, 0, &eax, &ebx, &ecx, &edx);
+
+ return ((eax & (0x1U << 7)) != 0);
Please define macros for 0x6, and (0x1U << 7)

It is hard to understand w/o checking spec.

+}
+
void pm_write_dsdt(struct vmctx *ctx, int ncpu)
{
int i;
@@ -364,6 +409,18 @@ void pm_write_dsdt(struct vmctx *ctx, int ncpu)
}
}

+ if (is_hwp_enabled()) {
+ if (i == 0) {
+ dsdt_write_cpc();
+ } else {
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (^^PR00._CPC)");
+ dsdt_line(" }");
+ dsdt_line("");
+ }
+ }
Let's print a log by pr_info to shows the HWP is enabled or disabled.

+
dsdt_line(" }");
}
}







Re: [PATCH] dm: add _CPC to guest ACPI when HWP is enabled

Zhao, Yakui
 

On 2022/6/6 21:16, Zhou, Wu wrote:
When running WaaG, we need to enable HWP to boost performance in
some scenarios. But when HWP is enabled in BIOS, windows does not
turn on HWP driver automatically just like Linux does. It requires
_CPC table in ACPI as well.
The _CPC table contains information about the HWP baseline registers.
Those regs are defined as architectural MSRs, so they should be the
same on different CPU models. Thus we can hard code the _CPC table.
When we turn off HWP in BIOS, windows's HWP driver will still be loaded
based on the _CPC table. This will cause the guest fail to boot.
So here we need read CPUID first, only add _CPC when HWP is enabled.
Tracked-On: #7695
Signed-off-by: Wu Zhou <wu.zhou@...>
---
devicemodel/hw/platform/acpi/acpi_pm.c | 57 ++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/devicemodel/hw/platform/acpi/acpi_pm.c b/devicemodel/hw/platform/acpi/acpi_pm.c
index 5d953717ff..1e1a27b629 100644
--- a/devicemodel/hw/platform/acpi/acpi_pm.c
+++ b/devicemodel/hw/platform/acpi/acpi_pm.c
@@ -316,6 +316,51 @@ static int dsdt_write_pss(struct vmctx *ctx, int vcpu_id)
return 0;
}
+/* _CPC: Continuous Performance Control
+ * Hard code a V3 CPC table, describing HWP register interface.
+ */
+static void dsdt_write_cpc(void)
+{
+ dsdt_line("");
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (Package (0x17)");
+ dsdt_line(" {");
+ dsdt_line(" 0x17,");
+ dsdt_line(" 0x03,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x00000000000000CE, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E7, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E8, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x02, 0x01, 0x0000000000000777, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x01, 0x00, 0x0000000000000770, 0x04, )},");
+ dsdt_line(" One,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x0A, 0x20, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero");
+ dsdt_line(" })");
+ dsdt_line(" }");
+}
+
+static bool is_hwp_enabled(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+ do_cpuid(0x6, 0, &eax, &ebx, &ecx, &edx);
+
+ return ((eax & (0x1U << 7)) != 0);
+}
This is used to check whether the HWP is supported.
Can we use the function name of is_hwp_supported?

+
void pm_write_dsdt(struct vmctx *ctx, int ncpu)
{
int i;
@@ -364,6 +409,18 @@ void pm_write_dsdt(struct vmctx *ctx, int ncpu)
}
}
+ if (is_hwp_enabled()) {
+ if (i == 0) {
+ dsdt_write_cpc();
+ } else {
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (^^PR00._CPC)");
+ dsdt_line(" }");
+ dsdt_line("");
+ }
+ }
+
dsdt_line(" }");
}
}


Re: [PATCH] dm: add _CPC to guest ACPI when HWP is enabled

Victor Sun
 

Better to have a comment, that the patch has a pre-condition: host CPUID.06H:EAX.[7] can't be hidden by vCPUID of Service VM.

-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On
Behalf Of Zhou, Wu
Sent: Monday, June 6, 2022 9:17 PM
To: acrn-dev@...
Subject: [acrn-dev] [PATCH] dm: add _CPC to guest ACPI when HWP is
enabled

When running WaaG, we need to enable HWP to boost performance in some
scenarios. But when HWP is enabled in BIOS, windows does not turn on HWP
driver automatically just like Linux does. It requires _CPC table in ACPI as well.

The _CPC table contains information about the HWP baseline registers.
Those regs are defined as architectural MSRs, so they should be the same on
different CPU models. Thus we can hard code the _CPC table.

When we turn off HWP in BIOS, windows's HWP driver will still be loaded
based on the _CPC table. This will cause the guest fail to boot.
So here we need read CPUID first, only add _CPC when HWP is enabled.

Tracked-On: #7695
Signed-off-by: Wu Zhou <wu.zhou@...>
---
devicemodel/hw/platform/acpi/acpi_pm.c | 57
++++++++++++++++++++++++++
1 file changed, 57 insertions(+)

diff --git a/devicemodel/hw/platform/acpi/acpi_pm.c
b/devicemodel/hw/platform/acpi/acpi_pm.c
index 5d953717ff..1e1a27b629 100644
--- a/devicemodel/hw/platform/acpi/acpi_pm.c
+++ b/devicemodel/hw/platform/acpi/acpi_pm.c
@@ -316,6 +316,51 @@ static int dsdt_write_pss(struct vmctx *ctx, int
vcpu_id)
return 0;
}

+/* _CPC: Continuous Performance Control
+ * Hard code a V3 CPC table, describing HWP register interface.
+ */
+static void dsdt_write_cpc(void)
+{
+ dsdt_line("");
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (Package (0x17)");
+ dsdt_line(" {");
+ dsdt_line(" 0x17,");
+ dsdt_line(" 0x03,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x00, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x08, 0x00000000000000CE, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x10, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x18, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x08, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x10, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x00, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x08, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00,
0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00,
0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00,
0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40,
0x00, 0x00000000000000E7, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40,
0x00, 0x00000000000000E8, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x02,
0x01, 0x0000000000000777, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x01,
0x00, 0x0000000000000770, 0x04, )},");
+ dsdt_line(" One,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x0A,
0x20, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08,
0x18, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero");
+ dsdt_line(" })");
+ dsdt_line(" }");
+}
+
+static bool is_hwp_enabled(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+ do_cpuid(0x6, 0, &eax, &ebx, &ecx, &edx);
+
+ return ((eax & (0x1U << 7)) != 0);
+}
+
void pm_write_dsdt(struct vmctx *ctx, int ncpu) {
int i;
@@ -364,6 +409,18 @@ void pm_write_dsdt(struct vmctx *ctx, int ncpu)
}
}

+ if (is_hwp_enabled()) {
+ if (i == 0) {
+ dsdt_write_cpc();
+ } else {
+ dsdt_line(" Method (_CPC, 0,
NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (^^PR00._CPC)");
+ dsdt_line(" }");
+ dsdt_line("");
+ }
+ }
+
dsdt_line(" }");
}
}






[PATCH] dm: add _CPC to guest ACPI when HWP is enabled

Zhou, Wu
 

When running WaaG, we need to enable HWP to boost performance in
some scenarios. But when HWP is enabled in BIOS, windows does not
turn on HWP driver automatically just like Linux does. It requires
_CPC table in ACPI as well.

The _CPC table contains information about the HWP baseline registers.
Those regs are defined as architectural MSRs, so they should be the
same on different CPU models. Thus we can hard code the _CPC table.

When we turn off HWP in BIOS, windows's HWP driver will still be loaded
based on the _CPC table. This will cause the guest fail to boot.
So here we need read CPUID first, only add _CPC when HWP is enabled.

Tracked-On: #7695
Signed-off-by: Wu Zhou <wu.zhou@...>
---
devicemodel/hw/platform/acpi/acpi_pm.c | 57 ++++++++++++++++++++++++++
1 file changed, 57 insertions(+)

diff --git a/devicemodel/hw/platform/acpi/acpi_pm.c b/devicemodel/hw/platform/acpi/acpi_pm.c
index 5d953717ff..1e1a27b629 100644
--- a/devicemodel/hw/platform/acpi/acpi_pm.c
+++ b/devicemodel/hw/platform/acpi/acpi_pm.c
@@ -316,6 +316,51 @@ static int dsdt_write_pss(struct vmctx *ctx, int vcpu_id)
return 0;
}

+/* _CPC: Continuous Performance Control
+ * Hard code a V3 CPC table, describing HWP register interface.
+ */
+static void dsdt_write_cpc(void)
+{
+ dsdt_line("");
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (Package (0x17)");
+ dsdt_line(" {");
+ dsdt_line(" 0x17,");
+ dsdt_line(" 0x03,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x00000000000000CE, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000771, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E7, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E8, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x02, 0x01, 0x0000000000000777, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x01, 0x00, 0x0000000000000770, 0x04, )},");
+ dsdt_line(" One,");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x0A, 0x20, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000774, 0x04, )},");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero,");
+ dsdt_line(" Zero");
+ dsdt_line(" })");
+ dsdt_line(" }");
+}
+
+static bool is_hwp_enabled(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+ do_cpuid(0x6, 0, &eax, &ebx, &ecx, &edx);
+
+ return ((eax & (0x1U << 7)) != 0);
+}
+
void pm_write_dsdt(struct vmctx *ctx, int ncpu)
{
int i;
@@ -364,6 +409,18 @@ void pm_write_dsdt(struct vmctx *ctx, int ncpu)
}
}

+ if (is_hwp_enabled()) {
+ if (i == 0) {
+ dsdt_write_cpc();
+ } else {
+ dsdt_line(" Method (_CPC, 0, NotSerialized)");
+ dsdt_line(" {");
+ dsdt_line(" Return (^^PR00._CPC)");
+ dsdt_line(" }");
+ dsdt_line("");
+ }
+ }
+
dsdt_line(" }");
}
}


Re: [PATCH] hv: compile out unused function if CONFIG_MULTIBOOT2 is disabled

Eddie Dong
 

Acked-by: Eddie Dong <eddie.dong@...>

-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On
Behalf Of Calvin Zhang
Sent: Monday, May 30, 2022 6:57 PM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Cc: Calvin Zhang <calvinzhang.cool@...>
Subject: [acrn-dev] [PATCH] hv: compile out unused function if
CONFIG_MULTIBOOT2 is disabled

When CONFIG_MULTIBOOT2 is disabled,
'create_service_vm_efi_mmap_desc' is unused and build fails becuase [-
Werror=unused-function] is set.

boot/guest/bzimage_loader.c:188:17: error:
'create_service_vm_efi_mmap_desc' defined but not used [-Werror=unused-
function]
188 | static uint16_t create_service_vm_efi_mmap_desc(struct acrn_vm
*vm, struct efi_memory_desc *efi_mmap_desc)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors

Tracked-On: #7634
Signed-off-by: Calvin Zhang <calvinzhang.cool@...>
---
hypervisor/boot/guest/bzimage_loader.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/hypervisor/boot/guest/bzimage_loader.c
b/hypervisor/boot/guest/bzimage_loader.c
index a05f2a176..d55519657 100644
--- a/hypervisor/boot/guest/bzimage_loader.c
+++ b/hypervisor/boot/guest/bzimage_loader.c
@@ -182,6 +182,7 @@ static void *get_bzimage_kernel_load_addr(struct
acrn_vm *vm)
return load_addr;
}

+#ifdef CONFIG_MULTIBOOT2
/**
* @pre vm != NULL && efi_mmap_desc != NULL
*/
@@ -234,6 +235,7 @@ static uint16_t
create_service_vm_efi_mmap_desc(struct acrn_vm *vm, struct efi_m

return desc_idx;
}
+#endif

/**
* @pre zp != NULL && vm != NULL
--
2.30.2





Re: [PATCH] misc: modify the logic of generate HV_RAM_START

chenli.wei
 

On 6/2/2022 4:08 PM, Junjie Mao wrote:
Chenli Wei <chenli.wei@...> writes:

From: Chenli Wei <chenli.wei@...>

The current code assume that there must be an HV_RAM_START element in
the scenario and we will generate it if user have not set, the default
value of HV_RAM_START is 0x00400000 which cause an overlap issue.

This patch remove the requires of HV_RAM_START element, calculate
HV_RAM_SIZE and find a region of e820 to run the ACRN which start
address will be HV_RAM_START.

It is still valid if the user set HV_RAM_START by XMLs.

Signed-off-by: Chenli Wei <chenli.wei@...>
---
.../config_tools/hv_config/board_defconfig.py | 50 +------------------
misc/config_tools/library/common.py | 2 +-
misc/config_tools/schema/config.xsd | 2 +-
misc/config_tools/static_allocators/hv_ram.py | 49 ++++++++++++++++++
misc/config_tools/xforms/config_common.xsl | 5 ++
5 files changed, 57 insertions(+), 51 deletions(-)
create mode 100644 misc/config_tools/static_allocators/hv_ram.py

diff --git a/misc/config_tools/hv_config/board_defconfig.py b/misc/config_tools/hv_config/board_defconfig.py
index 5d47533af..65a198486 100644
--- a/misc/config_tools/hv_config/board_defconfig.py
+++ b/misc/config_tools/hv_config/board_defconfig.py
@@ -13,8 +13,6 @@ import common
DESC = """# Board defconfig generated by acrn-config tool
"""
-HV_RAM_SIZE_MAX = 0x40000000
-
MEM_ALIGN = 2 * common.SIZE_M
@@ -54,60 +52,14 @@ def get_serial_type():
def get_memory(hv_info, config):
- # this dictonary mapped with 'address start':'mem range'
- ram_range = {}
-
- post_launched_vm_num = 0
- for id in common.VM_TYPES:
- if common.VM_TYPES[id] in scenario_cfg_lib.VM_DB and \
- scenario_cfg_lib.VM_DB[common.VM_TYPES[id]]["load_type"] == "POST_LAUNCHED_VM":
- post_launched_vm_num += 1
- hv_ram_size = common.HV_BASE_RAM_SIZE + common.POST_LAUNCHED_VM_RAM_SIZE * post_launched_vm_num
-
- ivshmem_enabled = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "IVSHMEM", "IVSHMEM_ENABLED")
- total_shm_size = 0
- if ivshmem_enabled == 'y':
- raw_shmem_regions = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "IVSHMEM", "IVSHMEM_REGION")
- for raw_shm in raw_shmem_regions:
- if raw_shm is None or raw_shm.strip() == '':
- continue
- raw_shm_splited = raw_shm.split(',')
- if len(raw_shm_splited) == 3 and raw_shm_splited[0].strip() != '' \
- and raw_shm_splited[1].strip() != '' and len(raw_shm_splited[2].strip().split(':')) >= 1:
- try:
- size = raw_shm_splited[1].strip()
- int_size = int(size) * 0x100000
- total_shm_size += int_size
- except Exception as e:
- print(e)
-
- hv_ram_size += 2 * max(total_shm_size, 0x200000)
- if hv_ram_size > HV_RAM_SIZE_MAX:
- common.print_red("requested RAM size should be smaller then {}".format(HV_RAM_SIZE_MAX), err=True)
- err_dic["board config: total vm number error"] = \
- "requested RAM size should be smaller then {}".format(HV_RAM_SIZE_MAX)
- return err_dic
-
- # reseve 16M memory for hv sbuf, ramoops, etc.
- reserved_ram = 0x1000000
# We recommend to put hv ram start address high than 0x10000000 to
# reduce memory conflict with GRUB/Service VM Kernel.
hv_start_offset = 0x10000000
- total_size = reserved_ram + hv_ram_size
for start_addr in list(board_cfg_lib.USED_RAM_RANGE):
if hv_start_offset <= start_addr < 0x80000000:
del board_cfg_lib.USED_RAM_RANGE[start_addr]
- ram_range = board_cfg_lib.get_ram_range()
- avl_start_addr = board_cfg_lib.find_avl_memory(ram_range, str(total_size), hv_start_offset)
- hv_start_addr = int(avl_start_addr, 16) + int(hex(reserved_ram), 16)
- hv_start_addr = common.round_up(hv_start_addr, MEM_ALIGN)
- board_cfg_lib.USED_RAM_RANGE[hv_start_addr] = total_size
-
- if not hv_info.mem.hv_ram_start:
- print("CONFIG_HV_RAM_START={}".format(hex(hv_start_addr)), file=config)
- else:
- print("CONFIG_HV_RAM_START={}".format(hv_info.mem.hv_ram_start), file=config)
+ print("CONFIG_HV_RAM_START={}".format(hv_info.mem.hv_ram_start), file=config)
print("CONFIG_STACK_SIZE={}".format(hv_info.mem.stack_size), file=config)
print("CONFIG_IVSHMEM_ENABLED={}".format(hv_info.mem.ivshmem_enable), file=config)
diff --git a/misc/config_tools/library/common.py b/misc/config_tools/library/common.py
index 7ea12fa9d..24ece4bf3 100644
--- a/misc/config_tools/library/common.py
+++ b/misc/config_tools/library/common.py
@@ -45,7 +45,7 @@ MAX_VM_NUM = 16
MAX_VUART_NUM = 8
HV_BASE_RAM_SIZE = 0x1400000
-POST_LAUNCHED_VM_RAM_SIZE = 0x1000000
+VM_RAM_SIZE = 0x2800000
class MultiItem():
diff --git a/misc/config_tools/schema/config.xsd b/misc/config_tools/schema/config.xsd
index 07777522e..24a15877f 100644
--- a/misc/config_tools/schema/config.xsd
+++ b/misc/config_tools/schema/config.xsd
@@ -129,7 +129,7 @@
<xs:documentation>Specify the size of the memory stack in bytes for each physical CPU. For example, if you specify 8 kilobytes, each CPU will get its own 8-kilobyte stack.</xs:documentation>
</xs:annotation>
</xs:element>
- <xs:element name="HV_RAM_START" type="HexFormat" default="0x00400000">
+ <xs:element name="HV_RAM_START" type="HexFormat" default="0x00400000" minOccurs="0">
The default value seems to be useless here as you have logic in the
static allocator to determine one if it is not given.
Yes,  we could remove the default="0x00400000" and we need the minOccurs="0".

There was a schema error if we remove both the "default" and "minOccurs" parameters.


Re: [PATCH] misc: modify the logic of generate HV_RAM_START

Junjie Mao
 

Chenli Wei <chenli.wei@...> writes:

From: Chenli Wei <chenli.wei@...>

The current code assume that there must be an HV_RAM_START element in
the scenario and we will generate it if user have not set, the default
value of HV_RAM_START is 0x00400000 which cause an overlap issue.

This patch remove the requires of HV_RAM_START element, calculate
HV_RAM_SIZE and find a region of e820 to run the ACRN which start
address will be HV_RAM_START.

It is still valid if the user set HV_RAM_START by XMLs.

Signed-off-by: Chenli Wei <chenli.wei@...>
---
.../config_tools/hv_config/board_defconfig.py | 50 +------------------
misc/config_tools/library/common.py | 2 +-
misc/config_tools/schema/config.xsd | 2 +-
misc/config_tools/static_allocators/hv_ram.py | 49 ++++++++++++++++++
misc/config_tools/xforms/config_common.xsl | 5 ++
5 files changed, 57 insertions(+), 51 deletions(-)
create mode 100644 misc/config_tools/static_allocators/hv_ram.py

diff --git a/misc/config_tools/hv_config/board_defconfig.py b/misc/config_tools/hv_config/board_defconfig.py
index 5d47533af..65a198486 100644
--- a/misc/config_tools/hv_config/board_defconfig.py
+++ b/misc/config_tools/hv_config/board_defconfig.py
@@ -13,8 +13,6 @@ import common
DESC = """# Board defconfig generated by acrn-config tool
"""

-HV_RAM_SIZE_MAX = 0x40000000
-
MEM_ALIGN = 2 * common.SIZE_M


@@ -54,60 +52,14 @@ def get_serial_type():

def get_memory(hv_info, config):

- # this dictonary mapped with 'address start':'mem range'
- ram_range = {}
-
- post_launched_vm_num = 0
- for id in common.VM_TYPES:
- if common.VM_TYPES[id] in scenario_cfg_lib.VM_DB and \
- scenario_cfg_lib.VM_DB[common.VM_TYPES[id]]["load_type"] == "POST_LAUNCHED_VM":
- post_launched_vm_num += 1
- hv_ram_size = common.HV_BASE_RAM_SIZE + common.POST_LAUNCHED_VM_RAM_SIZE * post_launched_vm_num
-
- ivshmem_enabled = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "IVSHMEM", "IVSHMEM_ENABLED")
- total_shm_size = 0
- if ivshmem_enabled == 'y':
- raw_shmem_regions = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "IVSHMEM", "IVSHMEM_REGION")
- for raw_shm in raw_shmem_regions:
- if raw_shm is None or raw_shm.strip() == '':
- continue
- raw_shm_splited = raw_shm.split(',')
- if len(raw_shm_splited) == 3 and raw_shm_splited[0].strip() != '' \
- and raw_shm_splited[1].strip() != '' and len(raw_shm_splited[2].strip().split(':')) >= 1:
- try:
- size = raw_shm_splited[1].strip()
- int_size = int(size) * 0x100000
- total_shm_size += int_size
- except Exception as e:
- print(e)
-
- hv_ram_size += 2 * max(total_shm_size, 0x200000)
- if hv_ram_size > HV_RAM_SIZE_MAX:
- common.print_red("requested RAM size should be smaller then {}".format(HV_RAM_SIZE_MAX), err=True)
- err_dic["board config: total vm number error"] = \
- "requested RAM size should be smaller then {}".format(HV_RAM_SIZE_MAX)
- return err_dic
-
- # reseve 16M memory for hv sbuf, ramoops, etc.
- reserved_ram = 0x1000000
# We recommend to put hv ram start address high than 0x10000000 to
# reduce memory conflict with GRUB/Service VM Kernel.
hv_start_offset = 0x10000000
- total_size = reserved_ram + hv_ram_size
for start_addr in list(board_cfg_lib.USED_RAM_RANGE):
if hv_start_offset <= start_addr < 0x80000000:
del board_cfg_lib.USED_RAM_RANGE[start_addr]
- ram_range = board_cfg_lib.get_ram_range()
- avl_start_addr = board_cfg_lib.find_avl_memory(ram_range, str(total_size), hv_start_offset)
- hv_start_addr = int(avl_start_addr, 16) + int(hex(reserved_ram), 16)
- hv_start_addr = common.round_up(hv_start_addr, MEM_ALIGN)
- board_cfg_lib.USED_RAM_RANGE[hv_start_addr] = total_size
-
- if not hv_info.mem.hv_ram_start:
- print("CONFIG_HV_RAM_START={}".format(hex(hv_start_addr)), file=config)
- else:
- print("CONFIG_HV_RAM_START={}".format(hv_info.mem.hv_ram_start), file=config)

+ print("CONFIG_HV_RAM_START={}".format(hv_info.mem.hv_ram_start), file=config)
print("CONFIG_STACK_SIZE={}".format(hv_info.mem.stack_size), file=config)
print("CONFIG_IVSHMEM_ENABLED={}".format(hv_info.mem.ivshmem_enable), file=config)

diff --git a/misc/config_tools/library/common.py b/misc/config_tools/library/common.py
index 7ea12fa9d..24ece4bf3 100644
--- a/misc/config_tools/library/common.py
+++ b/misc/config_tools/library/common.py
@@ -45,7 +45,7 @@ MAX_VM_NUM = 16
MAX_VUART_NUM = 8

HV_BASE_RAM_SIZE = 0x1400000
-POST_LAUNCHED_VM_RAM_SIZE = 0x1000000
+VM_RAM_SIZE = 0x2800000

class MultiItem():

diff --git a/misc/config_tools/schema/config.xsd b/misc/config_tools/schema/config.xsd
index 07777522e..24a15877f 100644
--- a/misc/config_tools/schema/config.xsd
+++ b/misc/config_tools/schema/config.xsd
@@ -129,7 +129,7 @@
<xs:documentation>Specify the size of the memory stack in bytes for each physical CPU. For example, if you specify 8 kilobytes, each CPU will get its own 8-kilobyte stack.</xs:documentation>
</xs:annotation>
</xs:element>
- <xs:element name="HV_RAM_START" type="HexFormat" default="0x00400000">
+ <xs:element name="HV_RAM_START" type="HexFormat" default="0x00400000" minOccurs="0">
The default value seems to be useless here as you have logic in the
static allocator to determine one if it is not given.

--
Best Regards
Junjie Mao

<xs:annotation acrn:views="">
<xs:documentation>The 2MB-aligned starting physical address of the RAM region used by the hypervisor.</xs:documentation>
</xs:annotation>
diff --git a/misc/config_tools/static_allocators/hv_ram.py b/misc/config_tools/static_allocators/hv_ram.py
new file mode 100644
index 000000000..0e85cc082
--- /dev/null
+++ b/misc/config_tools/static_allocators/hv_ram.py
@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+#
+# Copyright (C) 2022 Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+import sys, os
+sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', 'library'))
+import common, board_cfg_lib, scenario_cfg_lib
+
+HV_RAM_SIZE_MAX = 0x40000000
+
+MEM_ALIGN = 2 * common.SIZE_M
+
+def fn(board_etree, scenario_etree, allocation_etree):
+ # this dictonary mapped with 'address start':'mem range'
+ ram_range = {}
+
+ vm_num = 0
+ vm_list = scenario_etree.xpath("//vm")
+ if vm_list is not None:
+ vm_num = len(vm_list)
+ hv_ram_size = common.HV_BASE_RAM_SIZE + common.VM_RAM_SIZE * vm_num
+ ivshmem_list = scenario_etree.xpath("//IVSHMEM_SIZE/text()")
+ total_shm_size = 0
+ for ram_size in ivshmem_list:
+ try:
+ total_shm_size += int(ram_size) * 0x100000
+ except Exception as e:
+ print(e)
+ hv_ram_size += 2 * max(total_shm_size, 0x200000)
+ assert(hv_ram_size <= HV_RAM_SIZE_MAX)
+ # reseve 16M memory for hv sbuf, ramoops, etc.
+ reserved_ram = 0x1000000
+ # We recommend to put hv ram start address high than 0x10000000 to
+ # reduce memory conflict with GRUB/SOS Kernel.
+ hv_start_offset = 0x10000000
+ total_size = reserved_ram + hv_ram_size
+ for start_addr in list(board_cfg_lib.USED_RAM_RANGE):
+ if hv_start_offset <= start_addr < 0x80000000:
+ del board_cfg_lib.USED_RAM_RANGE[start_addr]
+ ram_range = board_cfg_lib.get_ram_range()
+ avl_start_addr = board_cfg_lib.find_avl_memory(ram_range, str(total_size), hv_start_offset)
+ hv_start_addr = int(avl_start_addr, 16) + int(hex(reserved_ram), 16)
+ hv_start_addr = common.round_up(hv_start_addr, MEM_ALIGN)
+ board_cfg_lib.USED_RAM_RANGE[hv_start_addr] = total_size
+ common.append_node("/acrn-config/hv/MEMORY/HV_RAM_START", hex(hv_start_addr), allocation_etree)
+ common.append_node("/acrn-config/hv/MEMORY/HV_RAM_SIZE", hex(hv_ram_size), allocation_etree)
diff --git a/misc/config_tools/xforms/config_common.xsl b/misc/config_tools/xforms/config_common.xsl
index 3c951ced3..6af8c2c31 100644
--- a/misc/config_tools/xforms/config_common.xsl
+++ b/misc/config_tools/xforms/config_common.xsl
@@ -155,6 +155,11 @@
<xsl:with-param name="default" select="//allocation-data/acrn-config/hv/MEMORY/HV_RAM_START" />
</xsl:call-template>

+ <xsl:call-template name="integer-by-key">
+ <xsl:with-param name="key" select="'HV_RAM_SIZE'" />
+ <xsl:with-param name="default" select="//allocation-data/acrn-config/hv/MEMORY/HV_RAM_SIZE" />
+ </xsl:call-template>
+
<xsl:call-template name="integer-by-key">
<xsl:with-param name="key" select="'STACK_SIZE'" />
</xsl:call-template>


[PATCH] misc: modify the logic of generate HV_RAM_START

Chenli Wei
 

From: Chenli Wei <chenli.wei@...>

The current code assume that there must be an HV_RAM_START element in
the scenario and we will generate it if user have not set, the default
value of HV_RAM_START is 0x00400000 which cause an overlap issue.

This patch remove the requires of HV_RAM_START element, calculate
HV_RAM_SIZE and find a region of e820 to run the ACRN which start
address will be HV_RAM_START.

It is still valid if the user set HV_RAM_START by XMLs.

Signed-off-by: Chenli Wei <chenli.wei@...>
---
.../config_tools/hv_config/board_defconfig.py | 50 +------------------
misc/config_tools/library/common.py | 2 +-
misc/config_tools/schema/config.xsd | 2 +-
misc/config_tools/static_allocators/hv_ram.py | 49 ++++++++++++++++++
misc/config_tools/xforms/config_common.xsl | 5 ++
5 files changed, 57 insertions(+), 51 deletions(-)
create mode 100644 misc/config_tools/static_allocators/hv_ram.py

diff --git a/misc/config_tools/hv_config/board_defconfig.py b/misc/config_tools/hv_config/board_defconfig.py
index 5d47533af..65a198486 100644
--- a/misc/config_tools/hv_config/board_defconfig.py
+++ b/misc/config_tools/hv_config/board_defconfig.py
@@ -13,8 +13,6 @@ import common
DESC = """# Board defconfig generated by acrn-config tool
"""

-HV_RAM_SIZE_MAX = 0x40000000
-
MEM_ALIGN = 2 * common.SIZE_M


@@ -54,60 +52,14 @@ def get_serial_type():

def get_memory(hv_info, config):

- # this dictonary mapped with 'address start':'mem range'
- ram_range = {}
-
- post_launched_vm_num = 0
- for id in common.VM_TYPES:
- if common.VM_TYPES[id] in scenario_cfg_lib.VM_DB and \
- scenario_cfg_lib.VM_DB[common.VM_TYPES[id]]["load_type"] == "POST_LAUNCHED_VM":
- post_launched_vm_num += 1
- hv_ram_size = common.HV_BASE_RAM_SIZE + common.POST_LAUNCHED_VM_RAM_SIZE * post_launched_vm_num
-
- ivshmem_enabled = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "IVSHMEM", "IVSHMEM_ENABLED")
- total_shm_size = 0
- if ivshmem_enabled == 'y':
- raw_shmem_regions = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "IVSHMEM", "IVSHMEM_REGION")
- for raw_shm in raw_shmem_regions:
- if raw_shm is None or raw_shm.strip() == '':
- continue
- raw_shm_splited = raw_shm.split(',')
- if len(raw_shm_splited) == 3 and raw_shm_splited[0].strip() != '' \
- and raw_shm_splited[1].strip() != '' and len(raw_shm_splited[2].strip().split(':')) >= 1:
- try:
- size = raw_shm_splited[1].strip()
- int_size = int(size) * 0x100000
- total_shm_size += int_size
- except Exception as e:
- print(e)
-
- hv_ram_size += 2 * max(total_shm_size, 0x200000)
- if hv_ram_size > HV_RAM_SIZE_MAX:
- common.print_red("requested RAM size should be smaller then {}".format(HV_RAM_SIZE_MAX), err=True)
- err_dic["board config: total vm number error"] = \
- "requested RAM size should be smaller then {}".format(HV_RAM_SIZE_MAX)
- return err_dic
-
- # reseve 16M memory for hv sbuf, ramoops, etc.
- reserved_ram = 0x1000000
# We recommend to put hv ram start address high than 0x10000000 to
# reduce memory conflict with GRUB/Service VM Kernel.
hv_start_offset = 0x10000000
- total_size = reserved_ram + hv_ram_size
for start_addr in list(board_cfg_lib.USED_RAM_RANGE):
if hv_start_offset <= start_addr < 0x80000000:
del board_cfg_lib.USED_RAM_RANGE[start_addr]
- ram_range = board_cfg_lib.get_ram_range()
- avl_start_addr = board_cfg_lib.find_avl_memory(ram_range, str(total_size), hv_start_offset)
- hv_start_addr = int(avl_start_addr, 16) + int(hex(reserved_ram), 16)
- hv_start_addr = common.round_up(hv_start_addr, MEM_ALIGN)
- board_cfg_lib.USED_RAM_RANGE[hv_start_addr] = total_size
-
- if not hv_info.mem.hv_ram_start:
- print("CONFIG_HV_RAM_START={}".format(hex(hv_start_addr)), file=config)
- else:
- print("CONFIG_HV_RAM_START={}".format(hv_info.mem.hv_ram_start), file=config)

+ print("CONFIG_HV_RAM_START={}".format(hv_info.mem.hv_ram_start), file=config)
print("CONFIG_STACK_SIZE={}".format(hv_info.mem.stack_size), file=config)
print("CONFIG_IVSHMEM_ENABLED={}".format(hv_info.mem.ivshmem_enable), file=config)

diff --git a/misc/config_tools/library/common.py b/misc/config_tools/library/common.py
index 7ea12fa9d..24ece4bf3 100644
--- a/misc/config_tools/library/common.py
+++ b/misc/config_tools/library/common.py
@@ -45,7 +45,7 @@ MAX_VM_NUM = 16
MAX_VUART_NUM = 8

HV_BASE_RAM_SIZE = 0x1400000
-POST_LAUNCHED_VM_RAM_SIZE = 0x1000000
+VM_RAM_SIZE = 0x2800000

class MultiItem():

diff --git a/misc/config_tools/schema/config.xsd b/misc/config_tools/schema/config.xsd
index 07777522e..24a15877f 100644
--- a/misc/config_tools/schema/config.xsd
+++ b/misc/config_tools/schema/config.xsd
@@ -129,7 +129,7 @@
<xs:documentation>Specify the size of the memory stack in bytes for each physical CPU. For example, if you specify 8 kilobytes, each CPU will get its own 8-kilobyte stack.</xs:documentation>
</xs:annotation>
</xs:element>
- <xs:element name="HV_RAM_START" type="HexFormat" default="0x00400000">
+ <xs:element name="HV_RAM_START" type="HexFormat" default="0x00400000" minOccurs="0">
<xs:annotation acrn:views="">
<xs:documentation>The 2MB-aligned starting physical address of the RAM region used by the hypervisor.</xs:documentation>
</xs:annotation>
diff --git a/misc/config_tools/static_allocators/hv_ram.py b/misc/config_tools/static_allocators/hv_ram.py
new file mode 100644
index 000000000..0e85cc082
--- /dev/null
+++ b/misc/config_tools/static_allocators/hv_ram.py
@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+#
+# Copyright (C) 2022 Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+import sys, os
+sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', 'library'))
+import common, board_cfg_lib, scenario_cfg_lib
+
+HV_RAM_SIZE_MAX = 0x40000000
+
+MEM_ALIGN = 2 * common.SIZE_M
+
+def fn(board_etree, scenario_etree, allocation_etree):
+ # this dictonary mapped with 'address start':'mem range'
+ ram_range = {}
+
+ vm_num = 0
+ vm_list = scenario_etree.xpath("//vm")
+ if vm_list is not None:
+ vm_num = len(vm_list)
+ hv_ram_size = common.HV_BASE_RAM_SIZE + common.VM_RAM_SIZE * vm_num
+ ivshmem_list = scenario_etree.xpath("//IVSHMEM_SIZE/text()")
+ total_shm_size = 0
+ for ram_size in ivshmem_list:
+ try:
+ total_shm_size += int(ram_size) * 0x100000
+ except Exception as e:
+ print(e)
+ hv_ram_size += 2 * max(total_shm_size, 0x200000)
+ assert(hv_ram_size <= HV_RAM_SIZE_MAX)
+ # reseve 16M memory for hv sbuf, ramoops, etc.
+ reserved_ram = 0x1000000
+ # We recommend to put hv ram start address high than 0x10000000 to
+ # reduce memory conflict with GRUB/SOS Kernel.
+ hv_start_offset = 0x10000000
+ total_size = reserved_ram + hv_ram_size
+ for start_addr in list(board_cfg_lib.USED_RAM_RANGE):
+ if hv_start_offset <= start_addr < 0x80000000:
+ del board_cfg_lib.USED_RAM_RANGE[start_addr]
+ ram_range = board_cfg_lib.get_ram_range()
+ avl_start_addr = board_cfg_lib.find_avl_memory(ram_range, str(total_size), hv_start_offset)
+ hv_start_addr = int(avl_start_addr, 16) + int(hex(reserved_ram), 16)
+ hv_start_addr = common.round_up(hv_start_addr, MEM_ALIGN)
+ board_cfg_lib.USED_RAM_RANGE[hv_start_addr] = total_size
+ common.append_node("/acrn-config/hv/MEMORY/HV_RAM_START", hex(hv_start_addr), allocation_etree)
+ common.append_node("/acrn-config/hv/MEMORY/HV_RAM_SIZE", hex(hv_ram_size), allocation_etree)
diff --git a/misc/config_tools/xforms/config_common.xsl b/misc/config_tools/xforms/config_common.xsl
index 3c951ced3..6af8c2c31 100644
--- a/misc/config_tools/xforms/config_common.xsl
+++ b/misc/config_tools/xforms/config_common.xsl
@@ -155,6 +155,11 @@
<xsl:with-param name="default" select="//allocation-data/acrn-config/hv/MEMORY/HV_RAM_START" />
</xsl:call-template>

+ <xsl:call-template name="integer-by-key">
+ <xsl:with-param name="key" select="'HV_RAM_SIZE'" />
+ <xsl:with-param name="default" select="//allocation-data/acrn-config/hv/MEMORY/HV_RAM_SIZE" />
+ </xsl:call-template>
+
<xsl:call-template name="integer-by-key">
<xsl:with-param name="key" select="'STACK_SIZE'" />
</xsl:call-template>
--
2.25.1


Re: [PATCH v2] dm: vdisplay: terminate acrn-dm process when SDL init failed

Yu Wang
 

Acked-by: Wang, Yu1 <yu1.wang@...>

On Thu, Jun 02, 2022 at 01:23:56PM +0800, peng.p.sun@... wrote:
From: Sun Peng <peng.p.sun@...>

Virtual display is component which based on native window system.
This feature depended phisical monitor connected and graphic driver in
SOS running correctly. If these dependencies fail, it is a fatal error
for virtual display. We have to terminate the device model to let user
fix runtime environment issue for graphics.

Tracked-On: #7672
Signed-off-by: Sun Peng <peng.p.sun@...>
---
devicemodel/core/main.c | 5 ++++-
devicemodel/hw/vdisplay_sdl.c | 6 +++++-
devicemodel/include/vdisplay.h | 2 +-
3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/devicemodel/core/main.c b/devicemodel/core/main.c
index 299a38dee..0e3d77bfa 100644
--- a/devicemodel/core/main.c
+++ b/devicemodel/core/main.c
@@ -1045,7 +1045,10 @@ main(int argc, char *argv[])
}

if (gfx_ui) {
- gfx_ui_init();
+ if(gfx_ui_init()) {
+ pr_err("gfx ui initialize failed\n");
+ exit(1);
+ }
}

for (;;) {
diff --git a/devicemodel/hw/vdisplay_sdl.c b/devicemodel/hw/vdisplay_sdl.c
index dfad4c6a8..1c3eb1efa 100644
--- a/devicemodel/hw/vdisplay_sdl.c
+++ b/devicemodel/hw/vdisplay_sdl.c
@@ -1128,7 +1128,7 @@ vdpy_deinit(int handle)
return 0;
}

-void
+int
gfx_ui_init()
{
SDL_SysWMinfo info;
@@ -1141,6 +1141,7 @@ gfx_ui_init()

if (SDL_Init(SDL_INIT_VIDEO)) {
pr_err("Failed to Init SDL2 system");
+ return -1;
}

SDL_GetDisplayBounds(0, &disp_rect);
@@ -1150,6 +1151,7 @@ gfx_ui_init()
pr_err("Too small resolutions. Please check the "
" graphics system\n");
SDL_Quit();
+ return -1;
}

SDL_SetHint(SDL_HINT_GRAB_KEYBOARD, "1");
@@ -1170,6 +1172,8 @@ gfx_ui_init()
SDL_GL_SetAttribute(SDL_GL_ALPHA_SIZE, 8);

vdpy.s.is_ui_realized = true;
+
+ return 0;
}

void
diff --git a/devicemodel/include/vdisplay.h b/devicemodel/include/vdisplay.h
index 510e3e967..99506469b 100644
--- a/devicemodel/include/vdisplay.h
+++ b/devicemodel/include/vdisplay.h
@@ -84,7 +84,7 @@ struct cursor {
};

int vdpy_parse_cmd_option(const char *opts);
-void gfx_ui_init();
+int gfx_ui_init();
int vdpy_init();
void vdpy_get_display_info(int handle, struct display_info *info);
void vdpy_surface_set(int handle, struct surface *surf);
--
2.25.1


[PATCH v2] dm: vdisplay: terminate acrn-dm process when SDL init failed

Sun, Peng
 

From: Sun Peng <peng.p.sun@...>

Virtual display is component which based on native window system.
This feature depended phisical monitor connected and graphic driver in
SOS running correctly. If these dependencies fail, it is a fatal error
for virtual display. We have to terminate the device model to let user
fix runtime environment issue for graphics.

Tracked-On: #7672
Signed-off-by: Sun Peng <peng.p.sun@...>
---
devicemodel/core/main.c | 5 ++++-
devicemodel/hw/vdisplay_sdl.c | 6 +++++-
devicemodel/include/vdisplay.h | 2 +-
3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/devicemodel/core/main.c b/devicemodel/core/main.c
index 299a38dee..0e3d77bfa 100644
--- a/devicemodel/core/main.c
+++ b/devicemodel/core/main.c
@@ -1045,7 +1045,10 @@ main(int argc, char *argv[])
}

if (gfx_ui) {
- gfx_ui_init();
+ if(gfx_ui_init()) {
+ pr_err("gfx ui initialize failed\n");
+ exit(1);
+ }
}

for (;;) {
diff --git a/devicemodel/hw/vdisplay_sdl.c b/devicemodel/hw/vdisplay_sdl.c
index dfad4c6a8..1c3eb1efa 100644
--- a/devicemodel/hw/vdisplay_sdl.c
+++ b/devicemodel/hw/vdisplay_sdl.c
@@ -1128,7 +1128,7 @@ vdpy_deinit(int handle)
return 0;
}

-void
+int
gfx_ui_init()
{
SDL_SysWMinfo info;
@@ -1141,6 +1141,7 @@ gfx_ui_init()

if (SDL_Init(SDL_INIT_VIDEO)) {
pr_err("Failed to Init SDL2 system");
+ return -1;
}

SDL_GetDisplayBounds(0, &disp_rect);
@@ -1150,6 +1151,7 @@ gfx_ui_init()
pr_err("Too small resolutions. Please check the "
" graphics system\n");
SDL_Quit();
+ return -1;
}

SDL_SetHint(SDL_HINT_GRAB_KEYBOARD, "1");
@@ -1170,6 +1172,8 @@ gfx_ui_init()
SDL_GL_SetAttribute(SDL_GL_ALPHA_SIZE, 8);

vdpy.s.is_ui_realized = true;
+
+ return 0;
}

void
diff --git a/devicemodel/include/vdisplay.h b/devicemodel/include/vdisplay.h
index 510e3e967..99506469b 100644
--- a/devicemodel/include/vdisplay.h
+++ b/devicemodel/include/vdisplay.h
@@ -84,7 +84,7 @@ struct cursor {
};

int vdpy_parse_cmd_option(const char *opts);
-void gfx_ui_init();
+int gfx_ui_init();
int vdpy_init();
void vdpy_get_display_info(int handle, struct display_info *info);
void vdpy_surface_set(int handle, struct surface *surf);
--
2.25.1


Re: [PATCH v1] dm: vdisplay: terminate acrn-dm process when SDL init failed

Yu Wang
 

On Thu, Jun 02, 2022 at 12:09:36PM +0800, peng.p.sun@... wrote:
From: Sun Peng <peng.p.sun@...>

Virtual display is component which based on native window system.
This feature depended phisical monitor connected and graphic driver in
SOS running correctly. If these dependencies fail, it is a fatal error
for virtual display. We have to terminate the device model to let user
fix runtime environment issue for graphics.

Tracked-On: #7672
Signed-off-by: Sun Peng <peng.p.sun@...>
---
devicemodel/hw/vdisplay_sdl.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/devicemodel/hw/vdisplay_sdl.c b/devicemodel/hw/vdisplay_sdl.c
index dfad4c6a8..e6127f846 100644
--- a/devicemodel/hw/vdisplay_sdl.c
+++ b/devicemodel/hw/vdisplay_sdl.c
@@ -1141,6 +1141,7 @@ gfx_ui_init()

if (SDL_Init(SDL_INIT_VIDEO)) {
pr_err("Failed to Init SDL2 system");
+ exit(1);
Please return -1 and do exit(1) in main() with an error log.

}

SDL_GetDisplayBounds(0, &disp_rect);
--
2.25.1


[PATCH v1] dm: vdisplay: terminate acrn-dm process when SDL init failed

Sun, Peng
 

From: Sun Peng <peng.p.sun@...>

Virtual display is component which based on native window system.
This feature depended phisical monitor connected and graphic driver in
SOS running correctly. If these dependencies fail, it is a fatal error
for virtual display. We have to terminate the device model to let user
fix runtime environment issue for graphics.

Tracked-On: #7672
Signed-off-by: Sun Peng <peng.p.sun@...>
---
devicemodel/hw/vdisplay_sdl.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/devicemodel/hw/vdisplay_sdl.c b/devicemodel/hw/vdisplay_sdl.c
index dfad4c6a8..e6127f846 100644
--- a/devicemodel/hw/vdisplay_sdl.c
+++ b/devicemodel/hw/vdisplay_sdl.c
@@ -1141,6 +1141,7 @@ gfx_ui_init()

if (SDL_Init(SDL_INIT_VIDEO)) {
pr_err("Failed to Init SDL2 system");
+ exit(1);
}

SDL_GetDisplayBounds(0, &disp_rect);
--
2.25.1


Re: [PATCH] misc: Limit IVSHMEM region name to 27 characters

Liu, Yifan1
 

Sure. Will do.

-----Original Message-----
From: Mao, Junjie <junjie.mao@...>
Sent: Wednesday, June 1, 2022 5:00 PM
To: Liu, Yifan1 <yifan1.liu@...>
Cc: acrn-dev@...
Subject: Re: [acrn-dev] [PATCH] misc: Limit IVSHMEM region name to 27 characters

"Liu, Yifan1" <yifan1.liu@...> writes:

From: Yifan Liu <yifan1.liu@...>

Current IVSHMEM region name does not have size limit. This patch limits
it to 27 characters so that land specifier ("hv:/" or "dm:/") plus region
name can fit into an array of 32 characters.

Signed-off-by: Yifan Liu <yifan1.liu@...>
---
misc/config_tools/schema/types.xsd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/misc/config_tools/schema/types.xsd b/misc/config_tools/schema/types.xsd
index e4e7eefc0..9bfc62536 100644
--- a/misc/config_tools/schema/types.xsd
+++ b/misc/config_tools/schema/types.xsd
@@ -249,10 +249,10 @@ Read more about the available scheduling options in :ref:`cpu_sharing`.</xs:docu
</xs:annotation>
<xs:simpleType>
<xs:annotation>
- <xs:documentation>A string with no spaces.</xs:documentation>
+ <xs:documentation>A string with up to 27 characters of digits, letters and ``_``.</xs:documentation>
You may also want to update the placeholder of the corresponding
widget. IVSHMEM regions are configured using customized widgets. Thus,
the placeholder, i.e. the string in grey in the widget when users leave
it empty, is hardcoded in the vue file.

--
Best Regards
Junjie Mao

</xs:annotation>
<xs:restriction base="xs:string">
- <xs:pattern value="\w+" />
+ <xs:pattern value="\w{1,27}" />
</xs:restriction>
</xs:simpleType>
</xs:element>

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