Date   

Re: [PATCH v2] config_tools: set 'own_pcpu' of RTVM

Junjie Mao
 

-----Original Message-----
From: Zhao, Yuanyuan <yuanyuan.zhao@...>
Sent: Tuesday, November 29, 2022 8:40 AM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Subject: Re: [acrn-dev] [PATCH v2] config_tools: set 'own_pcpu' of RTVM

On 2022/11/28 10:26, Junjie Mao wrote:
-----Original Message-----
From: root <yuanyuan.zhao@...>
Sent: Monday, November 28, 2022 9:38 AM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Cc: yuanyuan.zhao@...
Subject: [PATCH v2] config_tools: set 'own_pcpu' of RTVM

From: Yuanyua Zhao <yuanyuan.zhao@...>

For STANDARD_VM 'own_pcpu' default value is 'n'. But RTVM always own pCPUs.
So check 'own_pcpu' of RTVM and make sure it's set to 'y'.

Signed-off-by: Yuanyua Zhao <yuanyuan.zhao@...>
---
.../configurator/pyodide/populateDefaultValues.py | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
index 23f22f37a..241a8263d 100644
--- a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
+++ b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
@@ -46,6 +46,10 @@ def main(scenario):
if name.text not in vmNames:
name.text = ""

+ own_pcpus = etree.findall(".//vm[vm_type = 'RTVM']/own_pcpu")
That `findall` method comes from `xml` package which may have less support for XPATH
than lxml. Just to double check, have you verified it in your own build?
Yes. The own_pcpu of RTVM in saved scenario.xml is 'y'.
OK. Thanks for confirmation.

Reviewed-by: Junjie Mao <junjie.mao@...>

---
Best Regards
Junjie Mao

---
Best Regards
Junjie Mao

+ for o in own_pcpus:
+ o.text = 'y'
+
result = tostring(obj.get("scenario_etree").getroot())
result = result.decode()
result = convert_result({
--
2.25.1





Re: [PATCH v2] config_tools: set 'own_pcpu' of RTVM

Zhao, Yuanyuan
 

On 2022/11/28 10:26, Junjie Mao wrote:
-----Original Message-----
From: root <yuanyuan.zhao@...>
Sent: Monday, November 28, 2022 9:38 AM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Cc: yuanyuan.zhao@...
Subject: [PATCH v2] config_tools: set 'own_pcpu' of RTVM

From: Yuanyua Zhao <yuanyuan.zhao@...>

For STANDARD_VM 'own_pcpu' default value is 'n'. But RTVM always own pCPUs.
So check 'own_pcpu' of RTVM and make sure it's set to 'y'.

Signed-off-by: Yuanyua Zhao <yuanyuan.zhao@...>
---
.../configurator/pyodide/populateDefaultValues.py | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
index 23f22f37a..241a8263d 100644
--- a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
+++ b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
@@ -46,6 +46,10 @@ def main(scenario):
if name.text not in vmNames:
name.text = ""

+ own_pcpus = etree.findall(".//vm[vm_type = 'RTVM']/own_pcpu")
That `findall` method comes from `xml` package which may have less support for XPATH than lxml. Just to double check, have you verified it in your own build?
Yes. The own_pcpu of RTVM in saved scenario.xml is 'y'.
---
Best Regards
Junjie Mao

+ for o in own_pcpus:
+ o.text = 'y'
+
result = tostring(obj.get("scenario_etree").getroot())
result = result.decode()
result = convert_result({
--
2.25.1


Re: [PATCH v2] config_tools: set 'own_pcpu' of RTVM

Junjie Mao
 

-----Original Message-----
From: root <yuanyuan.zhao@...>
Sent: Monday, November 28, 2022 9:38 AM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Cc: yuanyuan.zhao@...
Subject: [PATCH v2] config_tools: set 'own_pcpu' of RTVM

From: Yuanyua Zhao <yuanyuan.zhao@...>

For STANDARD_VM 'own_pcpu' default value is 'n'. But RTVM always own pCPUs.
So check 'own_pcpu' of RTVM and make sure it's set to 'y'.

Signed-off-by: Yuanyua Zhao <yuanyuan.zhao@...>
---
.../configurator/pyodide/populateDefaultValues.py | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
index 23f22f37a..241a8263d 100644
--- a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
+++ b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
@@ -46,6 +46,10 @@ def main(scenario):
if name.text not in vmNames:
name.text = ""

+ own_pcpus = etree.findall(".//vm[vm_type = 'RTVM']/own_pcpu")
That `findall` method comes from `xml` package which may have less support for XPATH than lxml. Just to double check, have you verified it in your own build?

---
Best Regards
Junjie Mao

+ for o in own_pcpus:
+ o.text = 'y'
+
result = tostring(obj.get("scenario_etree").getroot())
result = result.decode()
result = convert_result({
--
2.25.1


[PATCH v2] config_tools: set 'own_pcpu' of RTVM

Zhao, Yuanyuan
 

From: Yuanyua Zhao <yuanyuan.zhao@...>

For STANDARD_VM 'own_pcpu' default value is 'n'. But RTVM always own pCPUs.
So check 'own_pcpu' of RTVM and make sure it's set to 'y'.

Signed-off-by: Yuanyua Zhao <yuanyuan.zhao@...>
---
.../configurator/pyodide/populateDefaultValues.py | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/misc/config_tools/configurator/pyodide/populateDefaultValues.py b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
index 23f22f37a..241a8263d 100644
--- a/misc/config_tools/configurator/pyodide/populateDefaultValues.py
+++ b/misc/config_tools/configurator/pyodide/populateDefaultValues.py
@@ -46,6 +46,10 @@ def main(scenario):
if name.text not in vmNames:
name.text = ""

+ own_pcpus = etree.findall(".//vm[vm_type = 'RTVM']/own_pcpu")
+ for o in own_pcpus:
+ o.text = 'y'
+
result = tostring(obj.get("scenario_etree").getroot())
result = result.decode()
result = convert_result({
--
2.25.1


Re: [PATCH] asyncio: refine the setup ioctl

Yu Wang
 

Acked-by: Wang, Yu1 <yu1.wang@...>

-----Original Message-----
From: Chen, Conghui <conghui.chen@...>
Sent: Thursday, November 24, 2022 1:39 PM
To: acrn-dev@...
Cc: Wang, Yu1 <yu1.wang@...>; Li, Fei1 <fei1.li@...>; Chen,
Conghui <conghui.chen@...>
Subject: [PATCH] asyncio: refine the setup ioctl

Remove the common interface for sbuf setup, as it is not accept by kernel
side. Instead, use dedicate setup function for asyncio to init its sbuf.

Signed-off-by: Conghui <conghui.chen@...>
---
devicemodel/core/main.c | 2 +-
devicemodel/core/vmmapi.c | 11 +++--------
devicemodel/include/public/hsm_ioctl_defs.h | 14 +++-----------
devicemodel/include/vmmapi.h | 2 +-
4 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/devicemodel/core/main.c b/devicemodel/core/main.c index
135a6435c..fdcb0347e 100644
--- a/devicemodel/core/main.c
+++ b/devicemodel/core/main.c
@@ -850,7 +850,7 @@ vm_init_asyncio(struct vmctx *ctx, uint64_t base)
sbuf->overrun_cnt = 0;
sbuf->head = 0;
sbuf->tail = 0;
- return vm_setup_sbuf(ctx, ACRN_ASYNCIO, base);
+ return vm_setup_asyncio(ctx, base);
}

int
diff --git a/devicemodel/core/vmmapi.c b/devicemodel/core/vmmapi.c
index 43583eafc..0dbc1286e 100644
--- a/devicemodel/core/vmmapi.c
+++ b/devicemodel/core/vmmapi.c
@@ -295,19 +295,14 @@ vm_destroy(struct vmctx *ctx) }

int
-vm_setup_sbuf(struct vmctx *ctx, uint32_t sbuf_id, uint64_t base)
+vm_setup_asyncio(struct vmctx *ctx, uint64_t base)
{
int error;
- struct acrn_sbuf sbuf_param;

- bzero(&sbuf_param, sizeof(sbuf_param));
- sbuf_param.sbuf_id = sbuf_id;
- sbuf_param.base = base;
-
- error = ioctl(ctx->fd, ACRN_IOCTL_SETUP_SBUF, &sbuf_param);
+ error = ioctl(ctx->fd, ACRN_IOCTL_SETUP_ASYNCIO, base);

if (error) {
- pr_err("ACRN_IOCTL_SBUF_PAGE ioctl() returned an
error: %s\n", errormsg(errno));
+ pr_err("ACRN_IOCTL_SETUP_ASYNCIO ioctl() returned an
error: %s\n",
+errormsg(errno));
}

return error;
diff --git a/devicemodel/include/public/hsm_ioctl_defs.h
b/devicemodel/include/public/hsm_ioctl_defs.h
index 75656b2e5..c3230003f 100644
--- a/devicemodel/include/public/hsm_ioctl_defs.h
+++ b/devicemodel/include/public/hsm_ioctl_defs.h
@@ -107,8 +107,6 @@
_IOW(ACRN_IOCTL_TYPE, 0x41, struct acrn_vm_memmap)
#define ACRN_IOCTL_UNSET_MEMSEG \
_IOW(ACRN_IOCTL_TYPE, 0x42, struct acrn_vm_memmap)
-#define ACRN_IOCTL_SETUP_SBUF \
- _IOW(ACRN_IOCTL_TYPE, 0x43, struct acrn_sbuf)

/* PCI assignment*/
#define ACRN_IOCTL_SET_PTDEV_INTR \
@@ -138,6 +136,9 @@
#define ACRN_IOCTL_IRQFD \
_IOW(ACRN_IOCTL_TYPE, 0x71, struct acrn_irqfd)

+/* Asynchronous IO */
+#define ACRN_IOCTL_SETUP_ASYNCIO \
+ _IOW(ACRN_IOCTL_TYPE, 0x90, __u64)

#define ACRN_MEM_ACCESS_RIGHT_MASK 0x00000007U
#define ACRN_MEM_ACCESS_READ 0x00000001U
@@ -250,13 +251,4 @@ struct acrn_irqfd {
struct acrn_msi_entry msi;
};

-/**
- * @brief data structure to register a share buffer by ioctl
- */
-struct acrn_sbuf {
- /** Type of the sbuf. */
- uint32_t sbuf_id;
- /** Base address of the sbuf. */
- uint64_t base;
-};
#endif /* VHM_IOCTL_DEFS_H */
diff --git a/devicemodel/include/vmmapi.h
b/devicemodel/include/vmmapi.h index e9766e5f9..3109adc7f 100644
--- a/devicemodel/include/vmmapi.h
+++ b/devicemodel/include/vmmapi.h
@@ -107,7 +107,7 @@ int vm_create_ioreq_client(struct vmctx *ctx);
int vm_destroy_ioreq_client(struct vmctx *ctx);
int vm_attach_ioreq_client(struct vmctx *ctx);
int vm_notify_request_done(struct vmctx *ctx, int vcpu);
-int vm_setup_sbuf(struct vmctx *ctx, uint32_t sbuf_type, uint64_t
base);
+int vm_setup_asyncio(struct vmctx *ctx, uint64_t base);
void vm_clear_ioreq(struct vmctx *ctx);
const char *vm_state_to_str(enum vm_suspend_how idx);
void vm_set_suspend_mode(enum vm_suspend_how how);
--
2.25.1


[PATCH] asyncio: refine the setup ioctl

Conghui Chen
 

Remove the common interface for sbuf setup, as it is not accept by
kernel side. Instead, use dedicate setup function for asyncio to init
its sbuf.

Signed-off-by: Conghui <conghui.chen@...>
---
devicemodel/core/main.c | 2 +-
devicemodel/core/vmmapi.c | 11 +++--------
devicemodel/include/public/hsm_ioctl_defs.h | 14 +++-----------
devicemodel/include/vmmapi.h | 2 +-
4 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/devicemodel/core/main.c b/devicemodel/core/main.c
index 135a6435c..fdcb0347e 100644
--- a/devicemodel/core/main.c
+++ b/devicemodel/core/main.c
@@ -850,7 +850,7 @@ vm_init_asyncio(struct vmctx *ctx, uint64_t base)
sbuf->overrun_cnt = 0;
sbuf->head = 0;
sbuf->tail = 0;
- return vm_setup_sbuf(ctx, ACRN_ASYNCIO, base);
+ return vm_setup_asyncio(ctx, base);
}

int
diff --git a/devicemodel/core/vmmapi.c b/devicemodel/core/vmmapi.c
index 43583eafc..0dbc1286e 100644
--- a/devicemodel/core/vmmapi.c
+++ b/devicemodel/core/vmmapi.c
@@ -295,19 +295,14 @@ vm_destroy(struct vmctx *ctx)
}

int
-vm_setup_sbuf(struct vmctx *ctx, uint32_t sbuf_id, uint64_t base)
+vm_setup_asyncio(struct vmctx *ctx, uint64_t base)
{
int error;
- struct acrn_sbuf sbuf_param;

- bzero(&sbuf_param, sizeof(sbuf_param));
- sbuf_param.sbuf_id = sbuf_id;
- sbuf_param.base = base;
-
- error = ioctl(ctx->fd, ACRN_IOCTL_SETUP_SBUF, &sbuf_param);
+ error = ioctl(ctx->fd, ACRN_IOCTL_SETUP_ASYNCIO, base);

if (error) {
- pr_err("ACRN_IOCTL_SBUF_PAGE ioctl() returned an error: %s\n", errormsg(errno));
+ pr_err("ACRN_IOCTL_SETUP_ASYNCIO ioctl() returned an error: %s\n", errormsg(errno));
}

return error;
diff --git a/devicemodel/include/public/hsm_ioctl_defs.h b/devicemodel/include/public/hsm_ioctl_defs.h
index 75656b2e5..c3230003f 100644
--- a/devicemodel/include/public/hsm_ioctl_defs.h
+++ b/devicemodel/include/public/hsm_ioctl_defs.h
@@ -107,8 +107,6 @@
_IOW(ACRN_IOCTL_TYPE, 0x41, struct acrn_vm_memmap)
#define ACRN_IOCTL_UNSET_MEMSEG \
_IOW(ACRN_IOCTL_TYPE, 0x42, struct acrn_vm_memmap)
-#define ACRN_IOCTL_SETUP_SBUF \
- _IOW(ACRN_IOCTL_TYPE, 0x43, struct acrn_sbuf)

/* PCI assignment*/
#define ACRN_IOCTL_SET_PTDEV_INTR \
@@ -138,6 +136,9 @@
#define ACRN_IOCTL_IRQFD \
_IOW(ACRN_IOCTL_TYPE, 0x71, struct acrn_irqfd)

+/* Asynchronous IO */
+#define ACRN_IOCTL_SETUP_ASYNCIO \
+ _IOW(ACRN_IOCTL_TYPE, 0x90, __u64)

#define ACRN_MEM_ACCESS_RIGHT_MASK 0x00000007U
#define ACRN_MEM_ACCESS_READ 0x00000001U
@@ -250,13 +251,4 @@ struct acrn_irqfd {
struct acrn_msi_entry msi;
};

-/**
- * @brief data structure to register a share buffer by ioctl
- */
-struct acrn_sbuf {
- /** Type of the sbuf. */
- uint32_t sbuf_id;
- /** Base address of the sbuf. */
- uint64_t base;
-};
#endif /* VHM_IOCTL_DEFS_H */
diff --git a/devicemodel/include/vmmapi.h b/devicemodel/include/vmmapi.h
index e9766e5f9..3109adc7f 100644
--- a/devicemodel/include/vmmapi.h
+++ b/devicemodel/include/vmmapi.h
@@ -107,7 +107,7 @@ int vm_create_ioreq_client(struct vmctx *ctx);
int vm_destroy_ioreq_client(struct vmctx *ctx);
int vm_attach_ioreq_client(struct vmctx *ctx);
int vm_notify_request_done(struct vmctx *ctx, int vcpu);
-int vm_setup_sbuf(struct vmctx *ctx, uint32_t sbuf_type, uint64_t base);
+int vm_setup_asyncio(struct vmctx *ctx, uint64_t base);
void vm_clear_ioreq(struct vmctx *ctx);
const char *vm_state_to_str(enum vm_suspend_how idx);
void vm_set_suspend_mode(enum vm_suspend_how how);
--
2.25.1


Re: [PATCH] hv: support for pci uart with high mmio

hangliu1
 

On Mon, Nov 21, 2022 at 06:18:39PM +0000, Eddie Dong wrote:


-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On
Behalf Of hangliu1
Sent: Thursday, November 17, 2022 5:42 PM
To: Li, Fei1 <fei1.li@...>; acrn-dev@...
Cc: hangliu1 <hang1.liu@...>
Subject: [acrn-dev] [PATCH] hv: support for pci uart with high mmio

to enable early print output by pci uart, which has mmio address above 4G,
add the early pagetable map for the MMIO range.

we make an assumption that only map it with 2MB page, since platform with
39bit memory width have no 1G huge page feature and we cannot get the
capacity at runtime, since it is a very early code stage.

Signed-off-by: hangliu1 <hang1.liu@...>
---
hypervisor/debug/uart16550.c | 45 +++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 11 deletions(-)

diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
index 1d56ec190..9dad8152f 100644
--- a/hypervisor/debug/uart16550.c
+++ b/hypervisor/debug/uart16550.c
@@ -121,6 +121,30 @@ static void uart16550_set_baud_rate(uint32_t
baud_rate)
uart16550_write_reg(uart, temp_reg, UART16550_LCR); }

+static uint8_t uart_pde_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+static uint8_t uart_pdpte_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+
+static void early_pgtable_map_uart(uint64_t addr) {
+ uint64_t *pml4e, *pdpte, *pde;
+ uint64_t value;
+
+ CPU_CR_READ(cr3, &value);
+ /*assumpiton for map high mmio in early pagetable is that it is only used
for
+ 2MB page since 1G page may not available when memory width is
39bit */
+ pml4e = pml4e_offset((uint64_t *)value, addr);
+ if(!(*pml4e & PAGE_PRESENT)) {
+ *pml4e = (uint64_t)uart_pdpte_page +
(PAGE_PRESENT|PAGE_RW);
+ }
+ pdpte = pdpte_offset(pml4e, addr);
+ /*make assumption here that *pdpte is not present since not setup
+ in assemble code except adress below 4G, which must be ensured
not to
+ passed to this function*/
+ *(pdpte) = (uint64_t)uart_pde_page+ (PAGE_PRESENT|PAGE_RW);
+ pde = pde_offset(pdpte, addr);
+ *pde = (addr & PDE_MASK) +
(PAGE_PRESENT|PAGE_RW|PAGE_PSE); }
+
void uart16550_init(bool early_boot)
{
void *mmio_base_va = NULL;
@@ -154,19 +178,18 @@ void uart16550_init(bool early_boot)
uart.port_address = (uint16_t)(bar0 &
PCI_BASE_ADDRESS_IO_MASK);
uart.reg_width = 1;
pci_pdev_write_cfg(uart.bdf,
PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN);
- } else {
- uint32_t bar_hi =
pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
-
- /* Enable the PCI UART if the BAR is 32bit, or
64bit with 4GB- mmio space. */
- if (((bar0 & 0x7U) == 0U) || (((bar0 & 0x7U)
== 4U) && (bar_hi == 0U))) {
+ } else if (((bar0 & 0x7U) == 0U) || ((bar0 & 0x7U) ==
4U)) {
uart.type = MMIO;
- uart.mmio_base_vaddr =
hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK));
+ uint32_t bar_hi =
pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
+ uint64_t addr = (bar0 &
PCI_BASE_ADDRESS_MEM_MASK)|(((uint64_t)bar_hi) << 32U);
We only do this for 64 bit MMIO BAR. Not for 32 bit MMIO BAR though bar_hi is likely 0 for this case.
yes, but this patch is merged, it will be soon be modified by later patches regarding other uart
changes.

+ if (bar_hi != 0U) {
+
early_pgtable_map_uart(addr);
+ }
+ uart.mmio_base_vaddr =
hpa2hva_early(addr);
pci_pdev_write_cfg(uart.bdf,
PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN);
- } else {
- /* TODO: enable 64bit BAR with
4GB+ mmio space */
- uart.enabled = false;
- return;
- }
+ } else {
+ uart.enabled = false;
+ return;
}
}
}
--
2.25.1









Re: [PATCH] hv: support for pci uart with high mmio

Eddie Dong
 

-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On
Behalf Of hangliu1
Sent: Thursday, November 17, 2022 5:42 PM
To: Li, Fei1 <fei1.li@...>; acrn-dev@...
Cc: hangliu1 <hang1.liu@...>
Subject: [acrn-dev] [PATCH] hv: support for pci uart with high mmio

to enable early print output by pci uart, which has mmio address above 4G,
add the early pagetable map for the MMIO range.

we make an assumption that only map it with 2MB page, since platform with
39bit memory width have no 1G huge page feature and we cannot get the
capacity at runtime, since it is a very early code stage.

Signed-off-by: hangliu1 <hang1.liu@...>
---
hypervisor/debug/uart16550.c | 45 +++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 11 deletions(-)

diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
index 1d56ec190..9dad8152f 100644
--- a/hypervisor/debug/uart16550.c
+++ b/hypervisor/debug/uart16550.c
@@ -121,6 +121,30 @@ static void uart16550_set_baud_rate(uint32_t
baud_rate)
uart16550_write_reg(uart, temp_reg, UART16550_LCR); }

+static uint8_t uart_pde_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+static uint8_t uart_pdpte_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+
+static void early_pgtable_map_uart(uint64_t addr) {
+ uint64_t *pml4e, *pdpte, *pde;
+ uint64_t value;
+
+ CPU_CR_READ(cr3, &value);
+ /*assumpiton for map high mmio in early pagetable is that it is only used
for
+ 2MB page since 1G page may not available when memory width is
39bit */
+ pml4e = pml4e_offset((uint64_t *)value, addr);
+ if(!(*pml4e & PAGE_PRESENT)) {
+ *pml4e = (uint64_t)uart_pdpte_page +
(PAGE_PRESENT|PAGE_RW);
+ }
+ pdpte = pdpte_offset(pml4e, addr);
+ /*make assumption here that *pdpte is not present since not setup
+ in assemble code except adress below 4G, which must be ensured
not to
+ passed to this function*/
+ *(pdpte) = (uint64_t)uart_pde_page+ (PAGE_PRESENT|PAGE_RW);
+ pde = pde_offset(pdpte, addr);
+ *pde = (addr & PDE_MASK) +
(PAGE_PRESENT|PAGE_RW|PAGE_PSE); }
+
void uart16550_init(bool early_boot)
{
void *mmio_base_va = NULL;
@@ -154,19 +178,18 @@ void uart16550_init(bool early_boot)
uart.port_address = (uint16_t)(bar0 &
PCI_BASE_ADDRESS_IO_MASK);
uart.reg_width = 1;
pci_pdev_write_cfg(uart.bdf,
PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN);
- } else {
- uint32_t bar_hi =
pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
-
- /* Enable the PCI UART if the BAR is 32bit, or
64bit with 4GB- mmio space. */
- if (((bar0 & 0x7U) == 0U) || (((bar0 & 0x7U)
== 4U) && (bar_hi == 0U))) {
+ } else if (((bar0 & 0x7U) == 0U) || ((bar0 & 0x7U) ==
4U)) {
uart.type = MMIO;
- uart.mmio_base_vaddr =
hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK));
+ uint32_t bar_hi =
pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
+ uint64_t addr = (bar0 &
PCI_BASE_ADDRESS_MEM_MASK)|(((uint64_t)bar_hi) << 32U);
We only do this for 64 bit MMIO BAR. Not for 32 bit MMIO BAR though bar_hi is likely 0 for this case.

+ if (bar_hi != 0U) {
+
early_pgtable_map_uart(addr);
+ }
+ uart.mmio_base_vaddr =
hpa2hva_early(addr);
pci_pdev_write_cfg(uart.bdf,
PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN);
- } else {
- /* TODO: enable 64bit BAR with
4GB+ mmio space */
- uart.enabled = false;
- return;
- }
+ } else {
+ uart.enabled = false;
+ return;
}
}
}
--
2.25.1





Re: [PATCH] config_tools: expose own_pcpu to RTVM

Zhao, Yuanyuan
 

On 2022/11/18 13:20, Junjie Mao wrote:
-----Original Message-----
From: root <yuanyuan.zhao@...>
Sent: Friday, November 18, 2022 11:21 AM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Cc: yuanyuan.zhao@...
Subject: [PATCH] config_tools: expose own_pcpu to RTVM

From: Yuanyuan Zhao <yuanyuan.zhao@...>

Expose own_pcpu widget to RTVM. Fix the value to true for RTVM
always own pcpus.

Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@...>
---
.../pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)

diff --git
a/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
b/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
index 75939d193..4933ff3e6 100644
---
a/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
+++
b/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
@@ -3,7 +3,7 @@
<b>{{ uiOptions.title }}</b>
<div class="p-4">
<div v-if="defaultVal.pcpu && defaultVal.pcpu.length>0">
- <b-row v-if="is_std_vm">
+ <b-row>
<label>
<n-popover trigger="hover" placement="top-start" style="width: 500px">
<template #trigger>
@@ -146,7 +146,7 @@ export default {
return
window.getCurrentFormSchemaData().BasicConfigType.definitions.CPUAffinityConfiguration.pro
perties.pcpu_id
},
pcpu_owned() {
- return vueUtils.getPathVal(this.rootFormData, 'own_pcpu')
+ return this.is_std_vm ? vueUtils.getPathVal(this.rootFormData, 'own_pcpu') : 'y'
I think this line alone is sufficient to make the generated scenario XML read reasonable, which is the only concern as of now.
Or is there any other reason that we need the other two line of changes?
Next line make sure that the velue of own_pcpu don't change when user click the widget.

---
Best Regards
Junjie Mao

},
uiOptions() {
return formUtils.getUiOptions({
@@ -178,8 +178,7 @@ export default {
this.defaultVal.pcpu.splice(index + 1, 0, {pcpu_id: null, real_time_vcpu: "n"})
},
click_own_pcpu() {
- let newValue = this.pcpu_owned === 'y' ? 'n' : 'y';
- vueUtils.setPathVal(this.rootFormData, 'own_pcpu', newValue)
+ return this.is_std_vm ? (this.pcpu_owned === 'y' ? 'n' : 'y') : 'y'
},
removePCPU(index) {
if (this.defaultVal.pcpu.length === 1) {
--
2.25.1


Re: [PATCH v3] config-tools: board inspector exits if the VMD is configured

Junjie Mao
 

-----Original Message-----
From: Yang, Yu-chu <yu-chu.yang@...>
Sent: Friday, November 18, 2022 1:52 PM
To: acrn-dev@...
Cc: Mao, Junjie <junjie.mao@...>
Subject: [PATCH v3] config-tools: board inspector exits if the VMD is configured

From: yuchuyang <yu-chu.yang@...>

Board inspector does not support multiple PCI segment. Stop running and
throw out the message for user to disable VMD from BIOS setting.

v2->v3
Refine the logger message of check_pci_domains.

Tracked-On: #8327
Signed-off-by: yuchuyang <yu-chu.yang@...>
Reviewed-by: Junjie Mao <junjie.mao@...>

One wording comment below.

---
misc/config_tools/board_inspector/board_inspector.py | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/misc/config_tools/board_inspector/board_inspector.py
b/misc/config_tools/board_inspector/board_inspector.py
index 645f1b375..bf2d47b3d 100755
--- a/misc/config_tools/board_inspector/board_inspector.py
+++ b/misc/config_tools/board_inspector/board_inspector.py
@@ -83,10 +83,12 @@ def native_check():
"Only KVM or QEMU is supported. Unexpected results may occur.")

def check_pci_domains():
- root_buses = filter(lambda x: x.startswith("pci"), os.listdir("/sys/devices"))
- domain_ids = set(map(lambda x: x.split(":")[0].replace("pci", ""), root_buses))
+ root_buses = os.listdir("/sys/bus/pci/devices/")
+ domain_ids = set(map(lambda x: x.split(":")[0], root_buses))
if len(domain_ids) > 1:
- logger.fatal(f"ACRN does not support platforms with multiple PCI domains
{domain_ids}. Check if the BIOS has any configuration that consolidates those domains into
one.")
+ logger.fatal(f"ACRN does not support platforms with multiple PCI domains
{domain_ids}. " \
+ "Check if the BIOS has any configuration that consolidates those domains into one.
" \
+ "Known causes of multiple PCI domains include: VMD (Volume Management Device).")
State explicitly that the cause is "VMD being enabled".

sys.exit(1)

def bring_up_cores():
--
2.25.1


[PATCH v3] config-tools: board inspector exits if the VMD is configured

Yang, Yu-chu
 

From: yuchuyang <yu-chu.yang@...>

Board inspector does not support multiple PCI segment. Stop running and
throw out the message for user to disable VMD from BIOS setting.

v2->v3
Refine the logger message of check_pci_domains.

Tracked-On: #8327
Signed-off-by: yuchuyang <yu-chu.yang@...>
---
misc/config_tools/board_inspector/board_inspector.py | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/misc/config_tools/board_inspector/board_inspector.py b/misc/config_tools/board_inspector/board_inspector.py
index 645f1b375..bf2d47b3d 100755
--- a/misc/config_tools/board_inspector/board_inspector.py
+++ b/misc/config_tools/board_inspector/board_inspector.py
@@ -83,10 +83,12 @@ def native_check():
"Only KVM or QEMU is supported. Unexpected results may occur.")

def check_pci_domains():
- root_buses = filter(lambda x: x.startswith("pci"), os.listdir("/sys/devices"))
- domain_ids = set(map(lambda x: x.split(":")[0].replace("pci", ""), root_buses))
+ root_buses = os.listdir("/sys/bus/pci/devices/")
+ domain_ids = set(map(lambda x: x.split(":")[0], root_buses))
if len(domain_ids) > 1:
- logger.fatal(f"ACRN does not support platforms with multiple PCI domains {domain_ids}. Check if the BIOS has any configuration that consolidates those domains into one.")
+ logger.fatal(f"ACRN does not support platforms with multiple PCI domains {domain_ids}. " \
+ "Check if the BIOS has any configuration that consolidates those domains into one. " \
+ "Known causes of multiple PCI domains include: VMD (Volume Management Device).")
sys.exit(1)

def bring_up_cores():
--
2.25.1


Re: [PATCH] config_tools: expose own_pcpu to RTVM

Junjie Mao
 

-----Original Message-----
From: root <yuanyuan.zhao@...>
Sent: Friday, November 18, 2022 11:21 AM
To: Mao, Junjie <junjie.mao@...>; acrn-dev@...
Cc: yuanyuan.zhao@...
Subject: [PATCH] config_tools: expose own_pcpu to RTVM

From: Yuanyuan Zhao <yuanyuan.zhao@...>

Expose own_pcpu widget to RTVM. Fix the value to true for RTVM
always own pcpus.

Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@...>
---
.../pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)

diff --git
a/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
b/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
index 75939d193..4933ff3e6 100644
---
a/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
+++
b/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomW
idget/cpu_affinity.vue
@@ -3,7 +3,7 @@
<b>{{ uiOptions.title }}</b>
<div class="p-4">
<div v-if="defaultVal.pcpu && defaultVal.pcpu.length>0">
- <b-row v-if="is_std_vm">
+ <b-row>
<label>
<n-popover trigger="hover" placement="top-start" style="width: 500px">
<template #trigger>
@@ -146,7 +146,7 @@ export default {
return
window.getCurrentFormSchemaData().BasicConfigType.definitions.CPUAffinityConfiguration.pro
perties.pcpu_id
},
pcpu_owned() {
- return vueUtils.getPathVal(this.rootFormData, 'own_pcpu')
+ return this.is_std_vm ? vueUtils.getPathVal(this.rootFormData, 'own_pcpu') : 'y'
I think this line alone is sufficient to make the generated scenario XML read reasonable, which is the only concern as of now.

Or is there any other reason that we need the other two line of changes?

---
Best Regards
Junjie Mao

},
uiOptions() {
return formUtils.getUiOptions({
@@ -178,8 +178,7 @@ export default {
this.defaultVal.pcpu.splice(index + 1, 0, {pcpu_id: null, real_time_vcpu: "n"})
},
click_own_pcpu() {
- let newValue = this.pcpu_owned === 'y' ? 'n' : 'y';
- vueUtils.setPathVal(this.rootFormData, 'own_pcpu', newValue)
+ return this.is_std_vm ? (this.pcpu_owned === 'y' ? 'n' : 'y') : 'y'
},
removePCPU(index) {
if (this.defaultVal.pcpu.length === 1) {
--
2.25.1


[PATCH v2] hv: support for pci uart with high mmio

hangliu1
 

to enable early print output by pci uart, which has mmio address
above 4G, add the early pagetable map for the MMIO range.

we make an assumption that only map it with 2MB page, since platform
with 39bit memory width have no 1G huge page feature and we cannot
get the capacity at runtime, since it is a very early code stage.

v2->v1:
1. add hva2hpa_early
2. add process when *pdpte is not present

Signed-off-by: hangliu1 <hang1.liu@...>
---
hypervisor/debug/uart16550.c | 50 ++++++++++++++++++++++++++++--------
1 file changed, 39 insertions(+), 11 deletions(-)

diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
index 1d56ec190..c917acd6b 100644
--- a/hypervisor/debug/uart16550.c
+++ b/hypervisor/debug/uart16550.c
@@ -121,6 +121,35 @@ static void uart16550_set_baud_rate(uint32_t baud_rate)
uart16550_write_reg(uart, temp_reg, UART16550_LCR);
}

+static uint8_t uart_pde_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+static uint8_t uart_pdpte_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+
+static void early_pgtable_map_uart(uint64_t addr)
+{
+ uint64_t *pml4e, *pdpte, *pde;
+ uint64_t value;
+
+ CPU_CR_READ(cr3, &value);
+ /*assumpiton for map high mmio in early pagetable is that it is only used for
+ 2MB page since 1G page may not available when memory width is 39bit */
+ pml4e = pml4e_offset((uint64_t *)value, addr);
+ /* address is above 512G */
+ if(!(*pml4e & PAGE_PRESENT)) {
+ *pml4e = hva2hpa_early(uart_pdpte_page) + (PAGE_PRESENT|PAGE_RW);
+ }
+ pdpte = pdpte_offset(pml4e, addr);
+ if(!(*pdpte & PAGE_PRESENT)) {
+ *(pdpte) = hva2hpa_early(uart_pde_page) + (PAGE_PRESENT|PAGE_RW);
+ pde = pde_offset(pdpte, addr);
+ *pde = (addr & PDE_MASK) + (PAGE_PRESENT|PAGE_RW|PAGE_PSE);
+ } else if(!(*pdpte & PAGE_PSE)) {
+ pde = pde_offset(pdpte, addr);
+ if(!(*pde & PAGE_PRESENT)) {
+ *pde = (addr & PDE_MASK) + (PAGE_PRESENT|PAGE_RW|PAGE_PSE);
+ }
+ }
+}
+
void uart16550_init(bool early_boot)
{
void *mmio_base_va = NULL;
@@ -154,19 +183,18 @@ void uart16550_init(bool early_boot)
uart.port_address = (uint16_t)(bar0 & PCI_BASE_ADDRESS_IO_MASK);
uart.reg_width = 1;
pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN);
- } else {
- uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
-
- /* Enable the PCI UART if the BAR is 32bit, or 64bit with 4GB- mmio space. */
- if (((bar0 & 0x7U) == 0U) || (((bar0 & 0x7U) == 4U) && (bar_hi == 0U))) {
+ } else if (((bar0 & 0x7U) == 0U) || ((bar0 & 0x7U) == 4U)) {
uart.type = MMIO;
- uart.mmio_base_vaddr = hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK));
+ uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
+ uint64_t addr = (bar0 & PCI_BASE_ADDRESS_MEM_MASK)|(((uint64_t)bar_hi) << 32U);
+ if (bar_hi != 0U) {
+ early_pgtable_map_uart(addr);
+ }
+ uart.mmio_base_vaddr = hpa2hva_early(addr);
pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN);
- } else {
- /* TODO: enable 64bit BAR with 4GB+ mmio space */
- uart.enabled = false;
- return;
- }
+ } else {
+ uart.enabled = false;
+ return;
}
}
}
--
2.25.1


[PATCH] config_tools: expose own_pcpu to RTVM

Zhao, Yuanyuan
 

From: Yuanyuan Zhao <yuanyuan.zhao@...>

Expose own_pcpu widget to RTVM. Fix the value to true for RTVM
always own pcpus.

Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@...>
---
.../pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue b/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue
index 75939d193..4933ff3e6 100644
--- a/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue
+++ b/misc/config_tools/configurator/packages/configurator/src/pages/Config/ConfigForm/CustomWidget/cpu_affinity.vue
@@ -3,7 +3,7 @@
<b>{{ uiOptions.title }}</b>
<div class="p-4">
<div v-if="defaultVal.pcpu && defaultVal.pcpu.length>0">
- <b-row v-if="is_std_vm">
+ <b-row>
<label>
<n-popover trigger="hover" placement="top-start" style="width: 500px">
<template #trigger>
@@ -146,7 +146,7 @@ export default {
return window.getCurrentFormSchemaData().BasicConfigType.definitions.CPUAffinityConfiguration.properties.pcpu_id
},
pcpu_owned() {
- return vueUtils.getPathVal(this.rootFormData, 'own_pcpu')
+ return this.is_std_vm ? vueUtils.getPathVal(this.rootFormData, 'own_pcpu') : 'y'
},
uiOptions() {
return formUtils.getUiOptions({
@@ -178,8 +178,7 @@ export default {
this.defaultVal.pcpu.splice(index + 1, 0, {pcpu_id: null, real_time_vcpu: "n"})
},
click_own_pcpu() {
- let newValue = this.pcpu_owned === 'y' ? 'n' : 'y';
- vueUtils.setPathVal(this.rootFormData, 'own_pcpu', newValue)
+ return this.is_std_vm ? (this.pcpu_owned === 'y' ? 'n' : 'y') : 'y'
},
removePCPU(index) {
if (this.defaultVal.pcpu.length === 1) {
--
2.25.1


Re: [PATCH v2] config-tools: board inspector exits if the VMD is configured

Junjie Mao
 

-----Original Message-----
From: Yang, Yu-chu <yu-chu.yang@...>
Sent: Friday, November 18, 2022 10:46 AM
To: acrn-dev@...
Cc: Mao, Junjie <junjie.mao@...>
Subject: [PATCH v2] config-tools: board inspector exits if the VMD is configured

From: yuchuyang <yu-chu.yang@...>

Board inspector does not support multiple PCI segment. Stop running and
throw out the message for user to disable VMD from BIOS setting.

v1->v2
Refine check_pci_domains from board_inspector.py. Discard the change of
dmar.py.

Signed-off-by: yuchuyang <yu-chu.yang@...>
---
misc/config_tools/board_inspector/board_inspector.py | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/misc/config_tools/board_inspector/board_inspector.py
b/misc/config_tools/board_inspector/board_inspector.py
index 645f1b375..d32f71b26 100755
--- a/misc/config_tools/board_inspector/board_inspector.py
+++ b/misc/config_tools/board_inspector/board_inspector.py
@@ -83,10 +83,11 @@ def native_check():
"Only KVM or QEMU is supported. Unexpected results may occur.")

def check_pci_domains():
- root_buses = filter(lambda x: x.startswith("pci"), os.listdir("/sys/devices"))
- domain_ids = set(map(lambda x: x.split(":")[0].replace("pci", ""), root_buses))
+ root_buses = os.listdir("/sys/bus/pci/devices/")
+ domain_ids = set(map(lambda x: x.split(":")[0], root_buses))
if len(domain_ids) > 1:
- logger.fatal(f"ACRN does not support platforms with multiple PCI domains
{domain_ids}. Check if the BIOS has any configuration that consolidates those domains into
one.")
+ logger.fatal(f"ACRN does not support platforms with multiple PCI domains
{domain_ids}. " \
+ "Please disable VMD (Volume Management Device) from BIOS setting.")
VMD is not the only reason why we see multiple PCI domains. You can write something like "known causes of multiple PCI domains include:" followed by a list which only contains "VMD" for now.

---
Best Regards
Junjie Mao

sys.exit(1)

def bring_up_cores():
--
2.25.1


Re: [PATCH v1] config-tools: board inspector does not exit if a usb device is unplugged

Junjie Mao
 

-----Original Message-----
From: Yang, Yu-chu <yu-chu.yang@...>
Sent: Friday, November 18, 2022 10:42 AM
To: acrn-dev@...
Cc: Mao, Junjie <junjie.mao@...>
Subject: [PATCH v1] config-tools: board inspector does not exit if a usb device is
unplugged

From: yuchuyang <yu-chu.yang@...>

Board inspector may throw an error if a usb device is unplugged or
disconnected while extracting usb device information. Print out the
debug message and continue parsing.

Signed-off-by: yuchuyang <yu-chu.yang@...>
Reviewed-by: Junjie Mao <junjie.mao@...>

One minor comment below.

---
.../board_inspector/extractors/95-usb.py | 31 ++++++++++---------
1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/misc/config_tools/board_inspector/extractors/95-usb.py
b/misc/config_tools/board_inspector/extractors/95-usb.py
index 99daa256f..d22416c86 100644
--- a/misc/config_tools/board_inspector/extractors/95-usb.py
+++ b/misc/config_tools/board_inspector/extractors/95-usb.py
@@ -3,7 +3,7 @@
# SPDX-License-Identifier: BSD-3-Clause
#

-import os, re
+import os, re, logging

from extractors.helpers import add_child, get_node

@@ -17,17 +17,20 @@ def extract(args, board_etree):
if m:
d = m.group(0)
devpath = os.path.join(USB_DEVICES_PATH, d)
- with open(os.path.join(devpath, 'devnum'), 'r') as f:
- devnum = f.read().strip()
- with open(os.path.join(devpath, 'busnum'), 'r') as f:
- busnum = f.read().strip()
- cmd_out = os.popen('lsusb -s {b}:{d}'.format(b=busnum, d=devnum)).read()
- desc = cmd_out.split(':', maxsplit=1)[1].strip('\n')
-
- with open(devpath + '/port/firmware_node/path') as f:
- acpi_path = f.read().strip()
- usb_port_node = get_node(board_etree, f"//device[acpi_object='{acpi_path}']")
- if usb_port_node is not None:
- add_child(usb_port_node, "usb_device", location=d,
- description=d + desc)
+ try:
+ with open(os.path.join(devpath, 'devnum'), 'r') as f:
+ devnum = f.read().strip()
+ with open(os.path.join(devpath, 'busnum'), 'r') as f:
+ busnum = f.read().strip()
+ cmd_out = os.popen('lsusb -s {b}:{d}'.format(b=busnum, d=devnum)).read()
+ desc = cmd_out.split(':', maxsplit=1)[1].strip('\n')

+ with open(devpath + '/port/firmware_node/path') as f:
+ acpi_path = f.read().strip()
+ usb_port_node = get_node(board_etree,
f"//device[acpi_object='{acpi_path}']")
+ if usb_port_node is not None:
+ add_child(usb_port_node, "usb_device", location=d,
+ description=d + desc)
+ except Exception as e:
+ logging.debug(f"{e}: please check if a USB device has been removed form
usb port{d}.")
Add one space between `port` and `{d}`.

---
Best Regards
Junjie Mao

+ pass
--
2.25.1


[PATCH v2] config-tools: board inspector exits if the VMD is configured

Yang, Yu-chu
 

From: yuchuyang <yu-chu.yang@...>

Board inspector does not support multiple PCI segment. Stop running and
throw out the message for user to disable VMD from BIOS setting.

v1->v2
Refine check_pci_domains from board_inspector.py. Discard the change of
dmar.py.

Signed-off-by: yuchuyang <yu-chu.yang@...>
---
misc/config_tools/board_inspector/board_inspector.py | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/misc/config_tools/board_inspector/board_inspector.py b/misc/config_tools/board_inspector/board_inspector.py
index 645f1b375..d32f71b26 100755
--- a/misc/config_tools/board_inspector/board_inspector.py
+++ b/misc/config_tools/board_inspector/board_inspector.py
@@ -83,10 +83,11 @@ def native_check():
"Only KVM or QEMU is supported. Unexpected results may occur.")

def check_pci_domains():
- root_buses = filter(lambda x: x.startswith("pci"), os.listdir("/sys/devices"))
- domain_ids = set(map(lambda x: x.split(":")[0].replace("pci", ""), root_buses))
+ root_buses = os.listdir("/sys/bus/pci/devices/")
+ domain_ids = set(map(lambda x: x.split(":")[0], root_buses))
if len(domain_ids) > 1:
- logger.fatal(f"ACRN does not support platforms with multiple PCI domains {domain_ids}. Check if the BIOS has any configuration that consolidates those domains into one.")
+ logger.fatal(f"ACRN does not support platforms with multiple PCI domains {domain_ids}. " \
+ "Please disable VMD (Volume Management Device) from BIOS setting.")
sys.exit(1)

def bring_up_cores():
--
2.25.1


[PATCH v1] config-tools: board inspector does not exit if a usb device is unplugged

Yang, Yu-chu
 

From: yuchuyang <yu-chu.yang@...>

Board inspector may throw an error if a usb device is unplugged or
disconnected while extracting usb device information. Print out the
debug message and continue parsing.

Signed-off-by: yuchuyang <yu-chu.yang@...>
---
.../board_inspector/extractors/95-usb.py | 31 ++++++++++---------
1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/misc/config_tools/board_inspector/extractors/95-usb.py b/misc/config_tools/board_inspector/extractors/95-usb.py
index 99daa256f..d22416c86 100644
--- a/misc/config_tools/board_inspector/extractors/95-usb.py
+++ b/misc/config_tools/board_inspector/extractors/95-usb.py
@@ -3,7 +3,7 @@
# SPDX-License-Identifier: BSD-3-Clause
#

-import os, re
+import os, re, logging

from extractors.helpers import add_child, get_node

@@ -17,17 +17,20 @@ def extract(args, board_etree):
if m:
d = m.group(0)
devpath = os.path.join(USB_DEVICES_PATH, d)
- with open(os.path.join(devpath, 'devnum'), 'r') as f:
- devnum = f.read().strip()
- with open(os.path.join(devpath, 'busnum'), 'r') as f:
- busnum = f.read().strip()
- cmd_out = os.popen('lsusb -s {b}:{d}'.format(b=busnum, d=devnum)).read()
- desc = cmd_out.split(':', maxsplit=1)[1].strip('\n')
-
- with open(devpath + '/port/firmware_node/path') as f:
- acpi_path = f.read().strip()
- usb_port_node = get_node(board_etree, f"//device[acpi_object='{acpi_path}']")
- if usb_port_node is not None:
- add_child(usb_port_node, "usb_device", location=d,
- description=d + desc)
+ try:
+ with open(os.path.join(devpath, 'devnum'), 'r') as f:
+ devnum = f.read().strip()
+ with open(os.path.join(devpath, 'busnum'), 'r') as f:
+ busnum = f.read().strip()
+ cmd_out = os.popen('lsusb -s {b}:{d}'.format(b=busnum, d=devnum)).read()
+ desc = cmd_out.split(':', maxsplit=1)[1].strip('\n')

+ with open(devpath + '/port/firmware_node/path') as f:
+ acpi_path = f.read().strip()
+ usb_port_node = get_node(board_etree, f"//device[acpi_object='{acpi_path}']")
+ if usb_port_node is not None:
+ add_child(usb_port_node, "usb_device", location=d,
+ description=d + desc)
+ except Exception as e:
+ logging.debug(f"{e}: please check if a USB device has been removed form usb port{d}.")
+ pass
--
2.25.1


Re: [PATCH] hv: support for pci uart with high mmio

Li, Fei1
 

+static uint8_t uart_pde_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+static uint8_t uart_pdpte_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+
+static void early_pgtable_map_uart(uint64_t addr) {
+ uint64_t *pml4e, *pdpte, *pde;
+ uint64_t value;
+
+ CPU_CR_READ(cr3, &value);
+ /*assumpiton for map high mmio in early pagetable is that it is only used for
align
+ 2MB page since 1G page may not available when memory width is 39bit */
+ pml4e = pml4e_offset((uint64_t *)value, addr);
/* address is above 512G */
+ if(!(*pml4e & PAGE_PRESENT)) {
+ *pml4e = (uint64_t)uart_pdpte_page + (PAGE_PRESENT|PAGE_RW);
hva2hpa_early(uart_pdpte_page) + (PAGE_PRESENT | PAGE_RW);
+ }
+ pdpte = pdpte_offset(pml4e, addr);
align
+ /*make assumption here that *pdpte is not present since not setup
+ in assemble code except adress below 4G, which must be ensured not to
+ passed to this function*/
Add ASSERT here or add check whether pdpte is present here.
+ *(pdpte) = (uint64_t)uart_pde_page+ (PAGE_PRESENT|PAGE_RW);
hva2hpa_early(uart_pde_page)
+ pde = pde_offset(pdpte, addr);
+ *pde = (addr & PDE_MASK) + (PAGE_PRESENT|PAGE_RW|PAGE_PSE); }
+


[PATCH] hv: support for pci uart with high mmio

hangliu1
 

to enable early print output by pci uart, which has mmio address
above 4G, add the early pagetable map for the MMIO range.

we make an assumption that only map it with 2MB page, since platform
with 39bit memory width have no 1G huge page feature and we cannot
get the capacity at runtime, since it is a very early code stage.

Signed-off-by: hangliu1 <hang1.liu@...>
---
hypervisor/debug/uart16550.c | 45 +++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 11 deletions(-)

diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
index 1d56ec190..9dad8152f 100644
--- a/hypervisor/debug/uart16550.c
+++ b/hypervisor/debug/uart16550.c
@@ -121,6 +121,30 @@ static void uart16550_set_baud_rate(uint32_t baud_rate)
uart16550_write_reg(uart, temp_reg, UART16550_LCR);
}

+static uint8_t uart_pde_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+static uint8_t uart_pdpte_page[PAGE_SIZE]__aligned(PAGE_SIZE);
+
+static void early_pgtable_map_uart(uint64_t addr)
+{
+ uint64_t *pml4e, *pdpte, *pde;
+ uint64_t value;
+
+ CPU_CR_READ(cr3, &value);
+ /*assumpiton for map high mmio in early pagetable is that it is only used for
+ 2MB page since 1G page may not available when memory width is 39bit */
+ pml4e = pml4e_offset((uint64_t *)value, addr);
+ if(!(*pml4e & PAGE_PRESENT)) {
+ *pml4e = (uint64_t)uart_pdpte_page + (PAGE_PRESENT|PAGE_RW);
+ }
+ pdpte = pdpte_offset(pml4e, addr);
+ /*make assumption here that *pdpte is not present since not setup
+ in assemble code except adress below 4G, which must be ensured not to
+ passed to this function*/
+ *(pdpte) = (uint64_t)uart_pde_page+ (PAGE_PRESENT|PAGE_RW);
+ pde = pde_offset(pdpte, addr);
+ *pde = (addr & PDE_MASK) + (PAGE_PRESENT|PAGE_RW|PAGE_PSE);
+}
+
void uart16550_init(bool early_boot)
{
void *mmio_base_va = NULL;
@@ -154,19 +178,18 @@ void uart16550_init(bool early_boot)
uart.port_address = (uint16_t)(bar0 & PCI_BASE_ADDRESS_IO_MASK);
uart.reg_width = 1;
pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN);
- } else {
- uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
-
- /* Enable the PCI UART if the BAR is 32bit, or 64bit with 4GB- mmio space. */
- if (((bar0 & 0x7U) == 0U) || (((bar0 & 0x7U) == 4U) && (bar_hi == 0U))) {
+ } else if (((bar0 & 0x7U) == 0U) || ((bar0 & 0x7U) == 4U)) {
uart.type = MMIO;
- uart.mmio_base_vaddr = hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK));
+ uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
+ uint64_t addr = (bar0 & PCI_BASE_ADDRESS_MEM_MASK)|(((uint64_t)bar_hi) << 32U);
+ if (bar_hi != 0U) {
+ early_pgtable_map_uart(addr);
+ }
+ uart.mmio_base_vaddr = hpa2hva_early(addr);
pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN);
- } else {
- /* TODO: enable 64bit BAR with 4GB+ mmio space */
- uart.enabled = false;
- return;
- }
+ } else {
+ uart.enabled = false;
+ return;
}
}
}
--
2.25.1

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