-----Original Message-----
From: acrn-dev@... <acrn-dev@...> On
Behalf Of Zhao, Yuanyuan
Sent: Thursday, April 14, 2022 4:57 AM
To: Li, Fei1 <fei1.li@...>; acrn-dev@...
Cc: yuanyuan.zhao@...
Subject: [acrn-dev] [PATCH 2/5] hv: add register definition of mc146818 RTC

Add register definition of mc146818 RTC for hv.

Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@...>
---
hypervisor/include/dm/mc146818rtc.h | 91
+++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 hypervisor/include/dm/mc146818rtc.h

diff --git a/hypervisor/include/dm/mc146818rtc.h
b/hypervisor/include/dm/mc146818rtc.h
new file mode 100644
index 000000000..d559fa532
--- /dev/null
+++ b/hypervisor/include/dm/mc146818rtc.h
@@ -0,0 +1,91 @@
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this
software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS
``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)rtc.h 7.1 (Berkeley) 5/12/91
+ * $FreeBSD$
+ */
+
+#ifndef _I386_ISA_RTC_H_
+#define _I386_ISA_RTC_H_

+
+/*
+ * MC146818 RTC Register locations
+ */
+
+#define RTC_SEC 0x00 /* seconds */
+#define RTC_SECALRM 0x01 /* seconds alarm */
+#define RTC_MIN 0x02 /* minutes */
+#define RTC_MINALRM 0x03 /* minutes alarm */
+#define RTC_HRS 0x04 /* hours */
+#define RTC_HRSALRM 0x05 /* hours alarm */
+#define RTC_WDAY 0x06 /* week day */
+#define RTC_DAY 0x07 /* day of month */
+#define RTC_MONTH 0x08 /* month of year */
+#define RTC_YEAR 0x09 /* month of year */
+
+#define RTC_STATUSA 0x0a /* status register A */
+#define RTCSA_TUP 0x80 /* time update, don't look now */
+#define RTCSA_RESET 0x70 /* reset divider */
+#define RTCSA_DIVIDER 0x20 /* divider correct for 32768 Hz */
+#define RTCSA_8192 0x03 /* 8192 Hz interrupt */
+#define RTCSA_4096 0x04
+#define RTCSA_2048 0x05
+#define RTCSA_1024 0x06 /* default for profiling */
+#define RTCSA_PROF RTCSA_1024
+#define RTC_PROFRATE 1024
+#define RTCSA_512 0x07
+#define RTCSA_256 0x08
+#define RTCSA_128 0x09
+#define RTCSA_NOPROF RTCSA_128
+#define RTC_NOPROFRATE 128
+#define RTCSA_64 0x0a
+#define RTCSA_32 0x0b /* 32 Hz interrupt */
+
+#define RTC_STATUSB 0x0b /* status register B */
+#define RTCSB_DST 0x01 /* USA Daylight Savings Time enable */
+#define RTCSB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */
+#define RTCSB_BCD 0x04 /* 0 = BCD, 1 = Binary coded time */
+#define RTCSB_SQWE 0x08 /* 1 = output sqare wave at SQW
pin */
+#define RTCSB_UINTR 0x10 /* 1 = enable update-ended interrupt */
+#define RTCSB_AINTR 0x20 /* 1 = enable alarm interrupt */
+#define RTCSB_PINTR 0x40 /* 1 = enable periodic clock interrupt */
+#define RTCSB_HALT 0x80 /* stop clock updates */
+
+#define RTC_INTR 0x0c /* status register C (R) interrupt source */
+#define RTCIR_UPDATE 0x10 /* update intr */
+#define RTCIR_ALARM 0x20 /* alarm intr */
+#define RTCIR_PERIOD 0x40 /* periodic intr */
+#define RTCIR_INT 0x80 /* interrupt output signal */
+
+#define RTC_STATUSD 0x0d /* status register D (R) Lost Power */
+#define RTCSD_PWR 0x80 /* clock power OK */
+
+#endif /* _I386_ISA_RTC_H_ */
--
2.25.1