[RFC PATCH v3 4/6] hv: Add vlapic_has_pending_intr of apicv to check pending interrupts


Shuo A Liu
 

Sometimes HV wants to know if there are pending interrupts of one vcpu.
Add .has_pending_intr interface in acrn_apicv_ops and return the pending
interrupts status by check IRRs of apicv.

Signed-off-by: Shuo A Liu <shuo.a.liu@...>
---
hypervisor/arch/x86/guest/vlapic.c | 29 +++++++++++++++++++++++++++++
hypervisor/include/arch/x86/guest/vlapic.h | 2 ++
2 files changed, 31 insertions(+)

diff --git a/hypervisor/arch/x86/guest/vlapic.c b/hypervisor/arch/x86/guest/vlapic.c
index 8c79a4d..1c7bdfb 100644
--- a/hypervisor/arch/x86/guest/vlapic.c
+++ b/hypervisor/arch/x86/guest/vlapic.c
@@ -1745,6 +1745,11 @@ static bool ptapic_has_pending_delivery_intr(__unused struct acrn_vcpu *vcpu)
return false;
}

+static bool ptapic_has_pending_intr(__unused struct acrn_vcpu *vcpu)
+{
+ return false;
+}
+
static bool ptapic_invalid(__unused uint32_t offset)
{
return false;
@@ -1754,6 +1759,7 @@ static const struct acrn_apicv_ops ptapic_ops = {
.accept_intr = ptapic_accept_intr,
.inject_intr = ptapic_inject_intr,
.has_pending_delivery_intr = ptapic_has_pending_delivery_intr,
+ .has_pending_intr = ptapic_has_pending_intr,
.apic_read_access_may_valid = ptapic_invalid,
.apic_write_access_may_valid = ptapic_invalid,
.x2apic_read_msr_may_valid = ptapic_invalid,
@@ -2379,6 +2385,27 @@ bool vlapic_has_pending_delivery_intr(struct acrn_vcpu *vcpu)
return vlapic->ops->has_pending_delivery_intr(vcpu);
}

+static bool apicv_basic_has_pending_intr(struct acrn_vcpu *vcpu)
+{
+ struct acrn_vlapic *vlapic = vcpu_vlapic(vcpu);
+ uint32_t vector;
+
+ vector = vlapic_find_highest_irr(vlapic);
+
+ return vector != 0UL;
+}
+
+static bool apicv_advanced_has_pending_intr(struct acrn_vcpu *vcpu)
+{
+ return apicv_basic_has_pending_intr(vcpu);
+}
+
+bool vlapic_has_pending_intr(struct acrn_vcpu *vcpu)
+{
+ struct acrn_vlapic *vlapic = vcpu_vlapic(vcpu);
+ return vlapic->ops->has_pending_intr(vcpu);
+}
+
static bool apicv_basic_apic_read_access_may_valid(__unused uint32_t offset)
{
return true;
@@ -2592,6 +2619,7 @@ static const struct acrn_apicv_ops apicv_basic_ops = {
.accept_intr = apicv_basic_accept_intr,
.inject_intr = apicv_basic_inject_intr,
.has_pending_delivery_intr = apicv_basic_has_pending_delivery_intr,
+ .has_pending_intr = apicv_basic_has_pending_intr,
.apic_read_access_may_valid = apicv_basic_apic_read_access_may_valid,
.apic_write_access_may_valid = apicv_basic_apic_write_access_may_valid,
.x2apic_read_msr_may_valid = apicv_basic_x2apic_read_msr_may_valid,
@@ -2602,6 +2630,7 @@ static const struct acrn_apicv_ops apicv_advanced_ops = {
.accept_intr = apicv_advanced_accept_intr,
.inject_intr = apicv_advanced_inject_intr,
.has_pending_delivery_intr = apicv_advanced_has_pending_delivery_intr,
+ .has_pending_intr = apicv_advanced_has_pending_intr,
.apic_read_access_may_valid = apicv_advanced_apic_read_access_may_valid,
.apic_write_access_may_valid = apicv_advanced_apic_write_access_may_valid,
.x2apic_read_msr_may_valid = apicv_advanced_x2apic_read_msr_may_valid,
diff --git a/hypervisor/include/arch/x86/guest/vlapic.h b/hypervisor/include/arch/x86/guest/vlapic.h
index f271a4e..8feea92 100644
--- a/hypervisor/include/arch/x86/guest/vlapic.h
+++ b/hypervisor/include/arch/x86/guest/vlapic.h
@@ -100,6 +100,7 @@ struct acrn_apicv_ops {
void (*accept_intr)(struct acrn_vlapic *vlapic, uint32_t vector, bool level);
bool (*inject_intr)(struct acrn_vlapic *vlapic, bool guest_irq_enabled, bool injected);
bool (*has_pending_delivery_intr)(struct acrn_vcpu *vcpu);
+ bool (*has_pending_intr)(struct acrn_vcpu *vcpu);
bool (*apic_read_access_may_valid)(uint32_t offset);
bool (*apic_write_access_may_valid)(uint32_t offset);
bool (*x2apic_read_msr_may_valid)(uint32_t offset);
@@ -118,6 +119,7 @@ void vlapic_set_apicv_ops(void);

bool vlapic_inject_intr(struct acrn_vlapic *vlapic, bool guest_irq_enabled, bool injected);
bool vlapic_has_pending_delivery_intr(struct acrn_vcpu *vcpu);
+bool vlapic_has_pending_intr(struct acrn_vcpu *vcpu);

/**
* @brief Get physical address to PIR description.
--
2.8.3

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