-----Original Message-----
From: acrn-dev@... [mailto:acrn-dev@...] On Behalf Of Grandhi, Sainath
Sent: Tuesday, March 5, 2019 2:20 PM
To: acrn-dev@...; Grandhi, Sainath <sainath.grandhi@...>
Subject: [acrn-dev] [PATCH] hv: Remove multiple definitions for dmar translation structures

Except for few translation structures in x86 IOMMU, all translation
structures are 128-bit. All the translation structures used by ACRN
are 128 bit. So removed multiple definitions and defined a struct
that accomodates 128 bit entries.

Signed-off-by: Sainath Grandhi <sainath.grandhi@...>
---
hypervisor/arch/x86/vtd.c | 71 +++++++++++++++------------------------
hypervisor/include/arch/x86/vtd.h | 10 +++---
2 files changed, 34 insertions(+), 47 deletions(-)

diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c
index d29a20e4..47b3efde 100644
--- a/hypervisor/arch/x86/vtd.c
+++ b/hypervisor/arch/x86/vtd.c
@@ -141,21 +141,6 @@ struct dmar_drhd_rt {
uint32_t fault_state[IOMMU_FAULT_REGISTER_STATE_NUM]; /* 32bit registers */
};

-struct dmar_root_entry {
- uint64_t lower;
- uint64_t upper;
-};
-
-struct dmar_context_entry {
- uint64_t lower;
- uint64_t upper;
-};
-
-struct dmar_qi_desc {
- uint64_t lower;
- uint64_t upper;
-};
-
struct context_table {
struct page buses[CONFIG_IOMMU_BUS_NUM];
};
@@ -596,12 +581,12 @@ static struct dmar_drhd_rt *device_to_dmaru(uint16_t segment, uint8_t bus, uint8
return dmar_unit;
}

-static void dmar_issue_qi_request(struct dmar_drhd_rt *dmar_unit, struct dmar_qi_desc invalidate_desc)
+static void dmar_issue_qi_request(struct dmar_drhd_rt *dmar_unit, struct dmar_entry invalidate_desc)
{
- struct dmar_qi_desc *invalidate_desc_ptr;
+ struct dmar_entry *invalidate_desc_ptr;
__unused uint64_t start;

- invalidate_desc_ptr = (struct dmar_qi_desc *)(dmar_unit->qi_queue + dmar_unit->qi_tail);
+ invalidate_desc_ptr = (struct dmar_entry *)(dmar_unit->qi_queue + dmar_unit->qi_tail);

invalidate_desc_ptr->upper = invalidate_desc.upper;
invalidate_desc_ptr->lower = invalidate_desc.lower;
@@ -637,7 +622,7 @@ static void dmar_issue_qi_request(struct dmar_drhd_rt *dmar_unit, struct dmar_qi
static void dmar_invalid_context_cache(struct dmar_drhd_rt *dmar_unit,
uint16_t did, uint16_t sid, uint8_t fm, enum dmar_cirg_type cirg)
{
- struct dmar_qi_desc invalidate_desc;
+ struct dmar_entry invalidate_desc;

invalidate_desc.upper = 0UL;
invalidate_desc.lower = DMAR_INV_CONTEXT_CACHE_DESC;
@@ -677,7 +662,7 @@ static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_unit, uint16_t did, uin
/* set Drain Reads & Drain Writes,
* if hardware doesn't support it, will be ignored by hardware
*/
- struct dmar_qi_desc invalidate_desc;
+ struct dmar_entry invalidate_desc;
uint64_t addr = 0UL;

invalidate_desc.upper = 0UL;
@@ -753,7 +738,7 @@ static void dmar_set_intr_remap_table(struct dmar_drhd_rt *dmar_unit)
static void dmar_invalid_iec(struct dmar_drhd_rt *dmar_unit, uint16_t intr_index,
uint8_t index_mask, bool is_global)
{
- struct dmar_qi_desc invalidate_desc;
+ struct dmar_entry invalidate_desc;

invalidate_desc.upper = 0UL;
invalidate_desc.lower = DMAR_INV_IEC_DESC;
@@ -899,7 +884,7 @@ static void dmar_fault_handler(uint32_t irq, void *data)
uint32_t fsr;
uint32_t index;
uint32_t record_reg_offset;
- uint64_t record[2];
+ struct dmar_entry fault_record;
int32_t loop = 0;

dev_dbg(ACRN_DBG_IOMMU, "%s: irq = %d", __func__, irq);
@@ -920,17 +905,17 @@ static void dmar_fault_handler(uint32_t irq, void *data)
}

/* read 128-bit fault recording register */
- record[0] = iommu_read64(dmar_unit, record_reg_offset);
- record[1] = iommu_read64(dmar_unit, record_reg_offset + 8U);
+ fault_record.lower = iommu_read64(dmar_unit, record_reg_offset);
+ fault_record.upper = iommu_read64(dmar_unit, record_reg_offset + 8U);

dev_dbg(ACRN_DBG_IOMMU, "%s: record[%d] @0x%x: 0x%llx, 0x%llx",
- __func__, index, record_reg_offset, record[0], record[1]);
+ __func__, index, record_reg_offset, fault_record.lower, fault_record.upper);

- fault_record_analysis(record[0], record[1]);
+ fault_record_analysis(fault_record.lower, fault_record.upper);

/* write to clear */
- iommu_write64(dmar_unit, record_reg_offset, record[0]);
- iommu_write64(dmar_unit, record_reg_offset + 8U, record[1]);
+ iommu_write64(dmar_unit, record_reg_offset, fault_record.lower);
+ iommu_write64(dmar_unit, record_reg_offset + 8U, fault_record.upper);

#ifdef DMAR_FAULT_LOOP_MAX
if (loop > DMAR_FAULT_LOOP_MAX) {
@@ -1049,11 +1034,11 @@ static void dmar_resume(struct dmar_drhd_rt *dmar_unit)
static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, uint8_t bus, uint8_t devfun)
{
struct dmar_drhd_rt *dmar_unit;
- struct dmar_root_entry *root_table;
+ struct dmar_entry *root_table;
uint64_t context_table_addr;
- struct dmar_context_entry *context;
- struct dmar_root_entry *root_entry;
- struct dmar_context_entry *context_entry;
+ struct dmar_entry *context;
+ struct dmar_entry *root_entry;
+ struct dmar_entry *context_entry;
uint64_t upper;
uint64_t lower = 0UL;
int32_t ret = 0;
@@ -1074,7 +1059,7 @@ static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, u
dev_dbg(ACRN_DBG_IOMMU, "vm=%d add %x:%x no snoop control!", domain->vm_id, bus, devfun);
}

- root_table = (struct dmar_root_entry *)hpa2hva(dmar_unit->root_table_addr);
+ root_table = (struct dmar_entry *)hpa2hva(dmar_unit->root_table_addr);

root_entry = root_table + bus;

@@ -1093,7 +1078,7 @@ static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, u

root_entry->upper = 0UL;
root_entry->lower = lower;
- iommu_flush_cache(dmar_unit, root_entry, sizeof(struct dmar_root_entry));
+ iommu_flush_cache(dmar_unit, root_entry, sizeof(struct dmar_entry));
} else {
context_table_addr = dmar_get_bitslice(root_entry->lower,
ROOT_ENTRY_LOWER_CTP_MASK, ROOT_ENTRY_LOWER_CTP_POS);
@@ -1101,7 +1086,7 @@ static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, u

context_table_addr = context_table_addr << PAGE_SHIFT;

- context = (struct dmar_context_entry *)hpa2hva(context_table_addr);
+ context = (struct dmar_entry *)hpa2hva(context_table_addr);
context_entry = context + devfun;

if (context_entry == NULL) {
@@ -1148,7 +1133,7 @@ static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, u

context_entry->upper = upper;
context_entry->lower = lower;
- iommu_flush_cache(dmar_unit, context_entry, sizeof(struct dmar_context_entry));
+ iommu_flush_cache(dmar_unit, context_entry, sizeof(struct dmar_entry));
}
}
}
@@ -1159,11 +1144,11 @@ static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, u
static int32_t remove_iommu_device(const struct iommu_domain *domain, uint16_t segment, uint8_t bus, uint8_t devfun)
{
struct dmar_drhd_rt *dmar_unit;
- struct dmar_root_entry *root_table;
+ struct dmar_entry *root_table;
uint64_t context_table_addr;
- struct dmar_context_entry *context;
- struct dmar_root_entry *root_entry;
- struct dmar_context_entry *context_entry;
+ struct dmar_entry *context;
+ struct dmar_entry *root_entry;
+ struct dmar_entry *context_entry;
int32_t ret = 0;

dmar_unit = device_to_dmaru(segment, bus, devfun);
@@ -1171,7 +1156,7 @@ static int32_t remove_iommu_device(const struct iommu_domain *domain, uint16_t s
pr_err("no dmar unit found for device: %x:%x.%x", bus, pci_slot(devfun), pci_func(devfun));
ret = -EINVAL;
} else {
- root_table = (struct dmar_root_entry *)hpa2hva(dmar_unit->root_table_addr);
+ root_table = (struct dmar_entry *)hpa2hva(dmar_unit->root_table_addr);
root_entry = root_table + bus;

if (root_entry == NULL) {
@@ -1180,7 +1165,7 @@ static int32_t remove_iommu_device(const struct iommu_domain *domain, uint16_t s
} else {
context_table_addr = dmar_get_bitslice(root_entry->lower, ROOT_ENTRY_LOWER_CTP_MASK,
ROOT_ENTRY_LOWER_CTP_POS);
context_table_addr = context_table_addr << PAGE_SHIFT;
- context = (struct dmar_context_entry *)hpa2hva(context_table_addr);
+ context = (struct dmar_entry *)hpa2hva(context_table_addr);

context_entry = context + devfun;

@@ -1194,7 +1179,7 @@ static int32_t remove_iommu_device(const struct iommu_domain *domain, uint16_t s
/* clear the present bit first */
context_entry->lower = 0UL;
context_entry->upper = 0UL;
- iommu_flush_cache(dmar_unit, context_entry, sizeof(struct dmar_context_entry));
+ iommu_flush_cache(dmar_unit, context_entry, sizeof(struct dmar_entry));

dmar_invalid_context_cache_global(dmar_unit);
dmar_invalid_iotlb_global(dmar_unit);
diff --git a/hypervisor/include/arch/x86/vtd.h b/hypervisor/include/arch/x86/vtd.h
index 01212248..f6d5e673 100644
--- a/hypervisor/include/arch/x86/vtd.h
+++ b/hypervisor/include/arch/x86/vtd.h
@@ -489,11 +489,13 @@ struct dmar_info {
struct dmar_drhd *drhd_units;
};

+struct dmar_entry {
+ uint64_t lower;
+ uint64_t upper;
+};
+
union dmar_ir_entry {
- struct {
- uint64_t lower;
- uint64_t upper;
- } entry;
+ struct dmar_entry entry;
struct {
uint64_t present:1;
uint64_t fpd:1;
--
2.14.1