From: Yin, Fengwei Sent: Wednesday, March 14, 2018 3:37 PM
On 03/14/2018 02:57 PM, Tian, Kevin wrote:
From: Dong, Eddie Sent: Wednesday, March 14, 2018 2:50 PM
Not sure if clear bit 63 is an architectural requirement or not.
+ Kevin.
I didn't understand. In 64bit mode, all 64bits are available. If bit63 is cleared how can you find a valid gpa for it?
Here is what I got: bit63 of the line address is actually not used for now. With 4-level paging, the PML4 entry is selected using: bits 51:12 from CR3 bits 11:3 are from bits 47:39 of liner address. bits 2:0 are all 0.
With 5-level paging, the PML5 entry is selected using: bits 51:12 are from CR3 bits 11:3 are bits 56:48 of the line address. bits 2:0 are all 0.
Also from "5-level paging and 5-Level EPT" White Paper: A linear address is 48-bit canonical if bits 63:47 of the address are identical. Similarly, an address is 57-bit canonical if bits 63:56 of the address are identical. Any linear address is that 48-bit canonical is also 57-bit canonical.
Thanks for confirmation. sorry I forgot there is canonical definition of available linear address bits. above info explains why kernel va can be 0xffffffffxxxxxxxx and yes anyway we don't need clear bit63 here. :-)
