Re: [PATCH 0/8] instruction decoding refine


Eddie Dong
 


In ACRN HV, only LAPIC and IOAPIC virtualization need instruction decoding.
The instructions to access LAPIC and IOAPIC are restrained. Can we only
decode instructions which are used to access LAPIC and IOAPIC and defer
other instruction decoding to SOS?
In this case, the DM needs to be able to inject #PF, #GP and walk guest page table....
And emulate the vCPU register operation.

That needs large change ...

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