Re: [PATCH 0/8] instruction decoding refine

Xu, Anthony

In ACRN HV, only LAPIC and IOAPIC virtualization need instruction decoding.
The instructions to access LAPIC and IOAPIC are restrained. Can we only decode
instructions which are used to access LAPIC and IOAPIC and defer other instruction decoding
to SOS?


-----Original Message-----
From: acrn-dev@... [mailto:acrn-dev@...]
On Behalf Of Yin, Fengwei
Sent: Tuesday, August 14, 2018 6:04 AM
To: acrn-dev@...
Subject: [acrn-dev] [PATCH 0/8] instruction decoding refine

According to SDM, we should check whether the gva access from
guest is valid. If it's not, correct exception should be injected.

We only need to emulate the instructions which access the
memory and could trigger EPT violation or APIC access VM exit.
It's not necessary to cover the instructions which doesn't access

To eliminate the side effect of access mmio, we move all gva check
to instruction decoding phase. To make instruction emulation always

There are two types of instructions:
- MOVS/STO. The gva is from DI/SI
- Others. The gva is from instruction decoding
We cover both of them.

The TODO work in next cyle refine:
- Fix issue in movs
- Optimize movs
- enable smep/smap check during gva2gpa
- cache the gpa during instruction decoding and avoid gva2gpa
during instruction emulation

Yin Fengwei (8):
hv: add lock prefix check for exception
hv: extend the decode_modrm
hv: fix use without initialization build error
hv: remove unnecessary check for gva
hv: move check out of vie_calculate_gla
hv: add new function to get gva for MOVS/STO instruction
hv: add failure case check for MOVS/STO
hv: add gva check for the case gva is from instruction decode

hypervisor/arch/x86/guest/instr_emul.c | 484 ++++++++++++++++---------
hypervisor/arch/x86/guest/instr_emul.h | 3 +-
2 files changed, 320 insertions(+), 167 deletions(-)


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