Re: [PATCH] drm/i915/gvt: fix display messy issue which is introduced by plane pvmmio


He, Min <min.he@...>
 

LGTM. But I don't think we need to talk about the reason of why it's missed in
previous patch.

Reviewed-by: He, Min <min.he@...>

-----Original Message-----
From: acrn-dev@... [mailto:acrn-dev@...]
On Behalf Of Fei Jiang
Sent: Monday, August 13, 2018 2:36 PM
To: acrn-dev@...
Cc: Jiang, Fei <fei.jiang@...>
Subject: [acrn-dev] [PATCH] drm/i915/gvt: fix display messy issue which is
introduced by plane pvmmio

For plane pvmmio optimization, we need cache all plane related registers,
in previous commit 9c3e8b1a3f15 ("drm/i915/gvt: handling pvmmio update
of
plane registers in GVT-g"), due to PLANE_AUX_DIST and PLANE_AUX_OFFSET
are
trapped with _REG_701C0 and _REG_701C4, then they are missing by only
checking PLANE_AUX_DIST and PLANE_AUX_OFFSET.

Signed-off-by: Fei Jiang <fei.jiang@...>
---
drivers/gpu/drm/i915/gvt/handlers.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index c33c771..6001127 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -777,6 +777,12 @@ static void pvmmio_update_plane_register(struct
intel_vgpu *vgpu,
skl_plane_mmio_write(vgpu,
i915_mmio_reg_offset(PLANE_SIZE(pipe, plane)),
&pv_plane->plane_size, 4);
+ skl_plane_mmio_write(vgpu,
+ i915_mmio_reg_offset(PLANE_AUX_DIST(pipe, plane)),
+ &pv_plane.plane_aux_dist, 4);
+ skl_plane_mmio_write(vgpu,
+ i915_mmio_reg_offset(PLANE_AUX_OFFSET(pipe, plane)),
+ &pv_plane.plane_aux_offset, 4);

if (pv_plane->flags & PLANE_SCALER_BIT) {
skl_ps_mmio_write(vgpu,
--
2.7.4


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